Author Topic: Programming (non-JTAG) MAX7000 devices  (Read 78174 times)

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Offline reverse

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #225 on: October 08, 2024, 09:30:06 am »
ADDED2: Looked briefly to ALL07 schematic... More complex and less understandable than ALL03.  :palm:

I own an ALL07C (a compact version of ALL07 with SMD components and built-in PAC_DIP40) for the past over 15 years, and unlike you, I like vintage programmers and I am almost daily using my ALL07C workhorse, of course it was a gift from a close friend of mine (damaged back then by automotive apps of his employers, obsolete, but to me very useful with vintage computers). Thanks to the French schematic on Matthieu's web site  (it has some minor errors, but these don't affect the overall understanding) and PLD equations I managed to succeed in almost fully controlling ALL07 via mine TASM DOS code. I haven't digged into ALL07 OSC generation control, but that is not interesting to me so far. That helped me with successfully dumping of vintage ROM PIC, and I have more plans for similar projects. I think I may be able to help you with understanding of ALL07 programmer. Alas, I have no HILO EPM adapters, I just handmade one, mentioned by me earlier in this topic, and it worked. I will be able to help with testing/debugging of your code on a real ALL07 programmer and Altera devices, should you need that.
« Last Edit: October 08, 2024, 09:46:16 am by reverse »
 
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Offline megov

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #226 on: October 09, 2024, 09:16:20 pm »
I think, that you don't understand me correctly. Maybe I write my thoughts not so clearly. English is not my native language.

I don't even try to blame vintage programmers, definitely. They're a good engineering devices of their own time. I just looked to schematic, that I've found at the same well-known and wonderful Matthieu's web site (it is not a joke, Matthieu's site is a very valuable source of information). And schematic, at least at the my first sight, seems to be much less understandable, than ALL03.

I'm not an owner of ALL07 and its lower/middle/higher boards structure was cumbersome.

Yes, later I found the functional dividing between sub-boards, more-or-less common (by function, not by exact schematic) blocks with ALL03 and pretty standard 4-bit scheme of "reading out" through various status bits of parallel port.

For my further intentions: I plan to analyze ALL07 schematic to understand its register map and where it differs from ALL03. I saw accesses to non-existent ALL03 registers in A70X.EXE.

Then I'll reverse A7064.EXE to trace actual interaction between software and ZIF socket pins. For this part of analysis it will be helpful to have @reverse adapter(s) pinouts. Thanks for support.

I have no plans to write 'software' to run with ALL03/ALL07. The idea is to understand the whole chain of technology (algorithms, interaction inside a programmer and how it connects to actual pins in various packages)
and describe it in simple terms and actions. This approach help to recreate parallel programmers functionality on modern basis.

And yes, it may help to erase/unlock hundreds of CPLDs that people have in their boxes.
 

Offline reverse

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #227 on: October 15, 2024, 07:12:28 am »
@Megov, I am quite skeptical about guys who announce what they plan to do prior to doing the job itself. I was just trying to widen your horizons of actions/tools and offer you more options. Neither the three PCBs of the ALL07 (ALL07C has only two PCBs, but the schematics is the same), nor the schematics are complicated at all. The reversing from PCBs was complicated, which the French guys already did without too much noise on forums.  If you experience  difficulties expressing yourself in English, I am also fluent in Russian.
 
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Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #228 on: October 16, 2024, 03:10:22 am »
My first steps in researching how it is possible to program an Altera EPM7032LC44-5, without using official tools.
Using a K6-2 500MHz PC with Windows 98, I managed to install MAX+PLus II version 9.3 from 1999.
I downloaded the files from a link on this forum.

I was able to activate the license. But I don't have any hardware to program EPLDs.

 
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Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #229 on: October 30, 2024, 03:09:53 am »
I have been studying about GAL, PAL and PLDs. I found these two CDs to download with various programs. Maybe there is something interesting.

For example:

"Welcome to Altera's FirstStep design kit, a free and simple
tool for easy PAL/GAL integration. FirstStep is a Windows
based utility program used to enter and compile designs for
Altera's EPM7032 high performance EPLD. "

https://archive.org/details/pld-start  (ISO.image)

Contents:
Altera: 1Step
Altera: PLDshell Plus
AMD: MachPro
AMD: MachXL
Data I/O: EasyABEL
Data I/O: Synario (Evaluation)
Isdata: LOG/IC (Evaluation)
Logical Devices: PALexpert
MicroSim: Design Center (Evaluation)
MicroSim + AMD: Design Center AMD (Evaluation)
National Semi: OPAL Jr
Quicklogic: pASIC
SH-Elektronik: GDS (Evaluation)
Texas Instruments: ProLOGIC
Xilinx: DS550
HiLo Systems: ALL07 programmer device list

https://archive.org/details/elrad-pld (ISO.image)

Contents:
Synario: ABEL-Edu 5.03
HiLo Systems: ALL-07 programmer device list
Minc-IST: Asyl+VHDL Starter Kit
Pilkington Micro: August Design System 2.2
Xilinx: DS550 6.0
Translogic: Ease-VHDL 2.3
Altera: First Step 1.0
Schuster/Belte: FPGA-Pilot (Evaluation)
SH-Elektronik: GDS 3.5 (Evaulation)
Mettner: GLSIM 1.10
Lattice: ISP Starter Kit  2.71
Isdata: LOG/IC2 4.22 (Evalation)
AMD: MachXL 2.1
AMD: MachXL/210 3.0
AMD: PALasm 1.5
Altera: PLDshell 5.0
MicroSim: PLSyn 6.2 (Evaluation)
iNT: PSI 2.1 (Evaluation)
iNT: SCAT 2.1a (Evaluation)
Visual Software Solutions: StateCAD 2.10F (Evaluation)
iNT: STC 2.1 (Evaluation)
iNT: SVU 1.0 (Evaluation)
iNT: VGEN 2.1 (Evaluation)
Cypress: Warp2/371 3.3
Xilinx: XABEL-CPLD 6.0 (Evaluation)

« Last Edit: October 30, 2024, 03:13:49 am by jgustavoam »
 
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Offline deanclaxton

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #230 on: November 04, 2024, 10:19:53 am »
Very interesting thread. Somewhat related, I'm working with Microchip ATF150x parts and would like to be able to set the security fuse to protect the design, however I'd also like to be able to erase and reprogram without removing the chip from the board.

Previously I've just been locking out the JTAG port, and using the +12V OE1 trick to re-enable it for reprogramming.

That trick is fairly well known now, so I think I need to start setting security however I'm yet to find a method to erase the device once the security is enabled other than desoldering the device and dropping it into my XELTEK 6100N. I'm using a ATDH1150USB-K programmer to re-program chips in system, however I'm using the XELTEK 6100N to initially program the devices pre-assembly.

Today I experimented a little with the securlty fuse. My Xeltek 6100N can set security, and then erase the device (removing security) no problem, however thats using a TQFP socket adapter in the programmer.

To date I've been unable to do this using the ATDH1150USB-K programmer.

I tried making an adapter today to go from the XELTEK 6100N to a TagConnect cable connecting the JTAG programming pins in an attempt to use the XELTEK to program a chip in-system - it didnt work. I got a message that it found an unrecognised 42 pin device. I also tried connecting OE1 through to the target board but it didnt help.

I wonder if the ATF150x do actually use parallel programming when in the XELTEK just like the EPM7000 series that (I believe) they are based on?

I guess I'll have to hook up a logic analyser to the XELTEK - maybe with some form of overvoltage protection on the OE1 pin. Are any other pins likely exposed to high voltage? I guess I may have to work around the socket with a CRO to check.



 
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Offline PCB.Wiz

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #231 on: November 04, 2024, 09:29:54 pm »
Very interesting thread. Somewhat related, I'm working with Microchip ATF150x parts and would like to be able to set the security fuse to protect the design, however I'd also like to be able to erase and reprogram without removing the chip from the board.

Previously I've just been locking out the JTAG port, and using the +12V OE1 trick to re-enable it for reprogramming.

That trick is fairly well known now, so I think I need to start setting security however I'm yet to find a method to erase the device once the security is enabled other than desoldering the device and dropping it into my XELTEK 6100N. I'm using a ATDH1150USB-K programmer to re-program chips in system, however I'm using the XELTEK 6100N to initially program the devices pre-assembly.

Today I experimented a little with the securlty fuse. My Xeltek 6100N can set security, and then erase the device (removing security) no problem, however thats using a TQFP socket adapter in the programmer.

To date I've been unable to do this using the ATDH1150USB-K programmer.
Did you try the 1150 to an ZIF adaptor ?

It seems strange the 1150 cannot bulk erase, my recollection is HV is needed only on VPP to enable JTAG and then all commands are available.
Maybe the in-circuit loadings affect Vcc ramp ?

When we did JTAG, I think we found short leads helped and 100R series termination helped reduce bounce effects

Minor point : IIRC some ATF150x parts need 11V Vpp, you could check what your Xeltek delivers ?

 
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Offline deanclaxton

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #232 on: November 04, 2024, 11:15:15 pm »
No - I havent tried a ZIF adapter driven by the ATDH1150. Hmmm. I can tweak the experimental adapter I built and add stacking headers - that way I could either drop it into the Xeltek OR I could plug a TQFP44 programming adapter into the top of it. Then rather than plug the TagConnect cable into the box header I put on it, I could plug in the ATDH1150. Doesn't help me though, but an interesting experiment.

Ultimately I need to find a way to re-program secure devices (ATF1502 and ATF1504) that are soldered down. EDIT - I really need to know whether this is even possible.

If you lock out the JTAG (in a lot of my designs I use the pins for other purposes) then you can reprogram via the ATDH1150 if you apply voltage to OE1 - that works fine with +12V applied. It doesn't work though if you set the security fuse. I am wondering if there is some way it can be done over JTAG in conjunction with maybe the OE1 pin if it was pulsed or something but I think I need to get a scope onto it to see what is going on there voltage wise as you suggest.
« Last Edit: November 04, 2024, 11:45:56 pm by deanclaxton »
 
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Offline deanclaxton

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #233 on: November 05, 2024, 02:02:17 am »
I don't mean to hijack the original thread - happy to start a separate topic for the ATF150x series if that is more appropriate.
 

Offline deanclaxton

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #234 on: November 05, 2024, 04:54:28 am »
Well, one simple question to forum's guru: am I right, that Altera MAX 7000S family devices (EPM7032SLC44, EPM7064SLC84, EPM7128SQI100, etc, etc, dozens of devices anyway) really support parallel programming mode? Yes, I know about their JTAG support and even use this kind of programming. Yes, I read somewhere, that JTAG can be disabled. Yes, I know that previous family (without S in suffix) does not support JTAG programming. So, am I right, that 7000S devices with disabled JTAG can be erased with parallel programmed and re-enable JTAG programming ability?

Or I'm insane and just trying to teach 7000S chip samples to accept parallel programming while they lack of it, like 3000S device series?

PS: I came to this theme by a simple reason - I own a whole tray (>60pcs) of new and unsoldered EPM7128SQI100-10 in rare and uncommon PQFP100/0.65 package (rectangle package, not square).
Even their actual pinout is a mystery: I only can find a single 6th pages PDF from Altera with EPM7128 pin correspondence between PLCC84, TQFP100 (square), PQFP100 (rectangle) and PQFP160 (again, square).
Two or three of them, being soldered to a interposer board do not answer to JTAG. So either I'm unable to trace JTAG pins, it is possible in this lack of information. Or they have JTAG disabled, that's why I'm here.
I love digital archaeology and reverse engineering, but fell that I'm exhausted here now...  :--

I'm wondering if ATF150x actually do support parallel programming also, and that is how the security fuse is removed and the device erased. I'll need to hook up my Xeltek programmer to the logic analyser though to test this.

Also the ramp of voltage from 10.2 to 12V - how fast is that ramp?
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #235 on: November 05, 2024, 09:27:24 pm »
EPM7032S - controlling JTAG support bit.

I'm first studying how to program the EPM7032S, and then trying to find out something about the EPM7032.
I learned how to program the EPM7032S with this guy. I am very grateful to him for his didactic guidance. I will test it as soon as my JTAG chips arrive.

https://youtu.be/1-oK0y2VH0Y?si=RiLJZ_ABhpBM2Yfm

https://github.com/marekl123/ezPLA-VHDL

I installed the Quartus II 64 bit - Version 13.0.1 program on my Windows 10 PC.

https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html

To enable the JTAG support bit, go to the Assignments / Device window and then click on Device and Pin Options. I think that's it.



« Last Edit: November 05, 2024, 09:30:10 pm by jgustavoam »
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #236 on: November 06, 2024, 12:39:33 am »
EPM7032S - Do I really need 12V to program?
I don't think so.

http://www.pldworld.com/_altera/html/toolman/cic.org.tw-alteratutorial.htm

MAX 7000S ISP
• MAX 7000S devices can be programmed through 4-pin JTAG interface

– By downloading the information via automatic test equipment, embedded
processors, or Altera BitBlaster/ByteBlaster download cable

MAX 7000S internally generates 12.0-V programming voltage

• Refer to Altera’s Application Brief & Application Note for details
– AB145 : Designing for In-System Programmability in MAX 7000S Devices
– AN039: JTAG Boundary-Scan Testing in Altera Devices

- AN100 In-System Programmability Guidelines
- AN095 In-System Programmability

« Last Edit: November 06, 2024, 03:03:06 pm by jgustavoam »
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #237 on: November 06, 2024, 02:14:34 am »
Trying to understand the structure of an EPM7032 and EPM7064.

"Note: the 7032 only has SCOA/SCOB, where as the 7064 has SCOA/B/C and D."

EPM7032 has 2 LABs.
EPM7064 has 4 LABs

Logic Array Blocks:

The MAX 7000 device architecture is based on the linking of high performance,flexible, logic array modules called logic array blocks (LABs).
LABs consist of 16-macrocell arrays.Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.

Each LAB is fed by the following signals:
■ 36 signals from the PIA that are used for general logic inputs
■ Global controls that are used for secondary register functions
■ Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices


« Last Edit: November 06, 2024, 02:18:34 am by jgustavoam »
 
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Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #238 on: November 22, 2024, 01:23:32 am »
EPM7032S programming

As I already mentioned, I am learning to use the EPM7032S first and then moving on to studying the EPM7032. The internal structures are similar.
I bought two used EPM7032SL44-10 chips. And an Altera USB Blaster clone module to program the chips.

USB Blaster Clone with CH552 chip:
https://www.eevblog.com/forum/fpga/usb-blaster-(ftdi245-vs-ch552x)-quartus-no-hardware/

Using Quartus 13.0 sp1 (32-bit) on an Intel Celeron PC / MB PCWare / Windows 7 (32-bit).
https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html

I used a 32-bit PC so that the environment would be as close to the reality of the 90s as possible.
My PC has a parallel printer port (LPT).

Using the example to program the EPM7032S: (Commodore 64 PLA replacement)
https://github.com/marekl123/ezPLA-VHDL

Several attempts to program both EPM7032s and neither of them were recognized. Searching in several forums and with some information from this forum, I discovered that my chips had JTAG locked.
Some pins on the JTAG interface were being blocked (digital signal less than 1V) because they were configured as output and not as signal input as they should be. For example, the TDI, TMS and TCK pins.
It may be a normal situation when the user intends to use the chip's JTAG interface pins in his circuit.
I believe that this same behavior can appear on chips without JTAG (EPM7032), if the programming mode is not activated.

Following the tips from this forum and others, I connected the OE1 pin (PLCC pin 44) to a 12V source using an 1K ohm resistor in series (a brief pulse of 12V).
I was able to unlock the JTAG interface of both chips with this procedure! But I am not supplying the chip with 12V during the programming procedure.

MAX7000S JTAG Lock:
https://www.vogons.org/viewtopic.php?t=100864
https://www.edaboard.com/threads/quartus-jtag-id-error-using-an-epm7128slc84-7-on-pldt-2-db.116711/
https://www.elektroda.com/rtvforum/topic3844129.html
https://forum.system-cfg.com/viewtopic.php?t=13192
https://community.intel.com/t5/Programmable-Devices/problem-programming-old-cpld-epm7032/td-p/156760


In the Quartus program, using the tool - JTAG Chain debugger, I can identify the chips as EPM7032S. (JTAG interface is working).
But, when I try to program I have received the following message:

"JTAG ID CODE SPECIFIED IN JEDEC STAPL FORMAT FILE DOESN'T MATCH ANY VALID JTAG ID CODES FOR DEVICE."

I did the same tests using the "Byte Blaster MV" interface (connected with parallel port LPT1) that I built on a protoboard. And the results were the same.

I assume I managed to unlock the JTAG interface of the chips, but I haven't been able to erase the original programming yet.

Reading numerous Altera documents, I saw that there is a procedure to erase the chip's memory. I know that using one of Altera's parallel programmers, it is possible to erase the memory.
But I don't have any of those rare and very expensive devices.
The research continues...

If you are interested in the ISP programming of the MAX7000S, I recommend reading the attached documents.

« Last Edit: November 22, 2024, 03:21:15 am by jgustavoam »
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #239 on: November 22, 2024, 08:25:06 pm »
EPM7032S - IDENTIFYING THE PINS

To find out and confirm that my EPM7032S chips had a blocked JTAG interface, I used a procedure based on the characteristics of the CPLD chip.
This procedure can also be used on other EPM7032 chips (without JTAG).

Measuring the JTAG interface signals (with scope) when I tried to program the EPM7032S, I noticed that some pins had a very low voltage level (below 1V).
Therefore, communication was blocked and the Quartus program could not recognize the chip.

Knowing that the maximum current on each pin can vary between +25 mA or -25 mA, I built this simple circuit, which helps identify whether the pin is an input or output.

Two 220 ohm resistors in series connected to GND and +5V.
The test lead to be connected to each pin of the chip must be connected between the two resistors.
To measure the test voltage with a voltmeter, connect its leads to the resistor connected to ground.
2443743-0

I filled a table with numerous voltage measurements on the pins of my chips in the state with the JTAG interface locked and then unlocked (see attached file).

To identify the pins, measure the voltage:
INPUT = 2.5V
OUTPUT LOW = 0.25 V
VCC = 5 V
GND = 0 V

2443747-1

Programming circuit to be attached to USB Blaster or Master Blaster MV (parallel Port LPT):

2443787-2



« Last Edit: November 22, 2024, 09:11:13 pm by jgustavoam »
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #240 on: December 12, 2024, 03:33:58 pm »
Deciphering EPM7032S erasure (trying):

The topic is quite large and I hadn't realized until yesterday that Pityokas had sent the records in the logic analyzer of the BEEPROG programmer, with some procedures performed with MAX7000 devices.

Thank you very much Pityokas, your records will be very useful for my analysis!

Programming Sequence for JTAG MAX7000S devices: (Datasheet)

1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms.

2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time.

3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms.

4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each
EEPROM address.

5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for
each EEPROM address.

6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms.


In parallel with studying EPLDs, I am also studying GAL devices, as for me they have similar characteristics.
I assembled this GAL programmer (with Arduino UNO) and managed to erase a Lattice GAL22V10B.

GAL chip programmer for Arduino:
https://github.com/ole00/afterburner

I used AfterBurner version 0.6.0 with this circuit that I edited (attached).
I was able to read the GAL26CV12B and the GAL22V10B. Including erasing it. But I still haven't been able to read the GAL16V8B.

* AfterBurner GAL Programmer Gustavo.pdf (219.14 kB - downloaded 60 times.)


See the 100ms pulse from the STRB pin that allows the GAL to be erased!

In the dark image attached.
2460017-1

For reference only:

GAL programming algorithms: (may be an inspiration for PLDs)
http://www.armory.com/%7Erstevew/Public/Pgmrs/GAL/algo.htm

Write, Erase, Security fuse (GAL16V8/GAL20V8) at VPP volt on EDIT:

Set P/V- to H, set up the desired pattern on RA0..RA5, apply first bit to SDIN, bring SCLK for a short time to H and back to L,
and transfer the next bit until all bits of this line have been transferred. Bring STB- to L and wait for the programming pulse time
before you take it back to H again. Restore P/V- to L at the end of the operation.


GAL22V10:

   1        2       4        8      16      32
/RA0  /RA1  /RA2   /RA3  /RA4  /RA5

    1       0       1        1       1        1      => 61 (0X3D) - CLEAR ?
 
     1       0       0       1       1        1       => 57 (0X39) - CLEAR ALL ?

   


 
« Last Edit: December 12, 2024, 08:51:22 pm by jgustavoam »
 

Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #241 on: December 12, 2024, 09:47:49 pm »
Analyzing EPM7032S erasure

Pityokas had sent the records in the logic analyzer of the BEEPROG programmer (aug/2022), with some procedures performed with MAX7000 devices.
Thank you very much Pityokas, your records are being very useful for my analysis!
https://www.eevblog.com/forum/fpga/programming-(non-jtag)-max7000-devices/msg4371268/#msg4371268

Analyzing file waveforms - epm7032s_erase.sr.
I changed the order of the lines for better understanding (attached file).
The 100ms pulse for erasure is evident!

VCC - active (5V)
VPP - active (5V or 12V ??)
NTPW - LOW pulse 100 ms
BE - HIGH pulse 100 ms
TM - HIGH pulse 100 ms
MT, MTIN - LOW
SS, SCK, SK - LOW
SDINA and SDINB - LOW 

A0   A1   A2   A3   A4   A5   A6
 1     1     0     1     1     1    0    = 0x3B (59)   CLEAR ALL ???

2460225-0

« Last Edit: December 13, 2024, 04:12:04 pm by jgustavoam »
 
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Offline jgustavoam

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #242 on: December 26, 2024, 02:00:46 am »
First attempt to erase EPM032S - failed

Based on Pityokas' logs, I assembled this circuit and program it with the Arduino Mega, to try to erase the EPM7032S.
Why did I use the Arduino Mega? Because it makes the circuit assembly easier. I like to simplify whenever possible.

Thinking that only the 100 millisecond interval would allow the EPM7032 to be erased, I did these tests. But I still couldn't erase it.

2470085-0

* EPM7032_prog.pdf (180.94 kB - downloaded 25 times.)

This is the INO code:
Code: [Select]
/* EPM7032S ERASE Programmer V0 - Arduino MEGA
PLD Altera EPM7032SLC44 in PROG MODE
Arduino IDE 2.3.4
Gustavo Murta - 2024/12/18

EDIT/VPP - PE4 (PIN02) = 12V control

NTPW - PL0 (PIN49) - bit value 0x01
BE   - PL1 (PIN48) - bit value 0x02
TM   - PL2 (PIN47) - bit value 0x04
MT   - PL3 (PIN46) - bit value 0x08
MTIN - PL4 (PIN45) - bit value 0x10

BEM  - PL6 (PIN43) - bit value 0x40
SBI  - PL7 (PIN42) - bit value 0x80

SS   - PC0 (PIN37) - bit value 0x01
SCK  - PC1 (PIN36) - bit value 0x02
SK   - PC2 (PIN35) - bit value 0x04

SDINA  - PC4 (PIN33) - bit value 0x10
SDOUTA - PB0 (PIN53) - bit value 0x01
SCOA   - PB1 (PIN52) - bit value 0x02

SDINB  - PC5 (PIN32) - bit value 0x20
SDOUTB - PB2 (PIN51) - bit value 0x04
SCOB   - PB3 (PIN50) - bit value 0x08

A6 - PA6 (PIN28) - bit value 0x40
A5 - PA5 (PIN27) - bit value 0x20
A4 - PA4 (PIN26) - bit value 0x10
A3 - PA3 (PIN25) - bit value 0x08
A2 - PA2 (PIN24) - bit value 0x04
A1 - PA1 (PIN23) - bit value 0x02
A0 - PA0 (PIN22) - bit value 0x01
*/

int count = 0;

void setup() {

  DDRA = 0xFF;         // configure PORTA pins as output
  DDRB = 0x00;         // configure PORTB pins as input
  DDRC = 0xFF;         // configure PORTC pins as output
  DDRL = 0xFF;         // configure PORTL pins as output
  pinMode(2, OUTPUT);  // configure PE4 as output (EDIT/VPP)

  PORTA = 0x00;          // SET all pins to LOW
  PORTC = 0x00;          // SET all pins to LOW
  PORTL = 0x00;          // SET all pins to LOW
  digitalWrite(2, LOW);  // set the digital pin PE4 LOW (EDIT/VPP)

  Serial.begin(115200);  // Monitor serial 115200 bps
  Serial.println("EPM7032S ERASE Programmer - press 'e' to chip erase ");
}

// ERASE EPM7032 sequence
void eraseEPM7032() {
  Serial.println("EPM7032S ERASE PULSE");
  PORTL = 0x06;  // set NTPW LOW , BE HIGH and TM HIGH
  delay(100);    // delay 100 miliseconds
  PORTL = 0x01;  // set NTPW HIGH - others LOW
  PORTA = 0x00;  // set Address 0x00 (A0 to A6 pins)
}

void loop() {

  while (Serial.available() > 0) {   // Verificar se há caracteres disponíveis
    char caractere = Serial.read();  // Armazena caractere lido
    if (caractere == 'e') {          // Verificar se o caractere é 'e'
      Serial.println("EPM7032S - Initialization process");
      PORTL = 0x01;           // set NTPW HIGH - others LOW
      delay(50);              // delay 50 miliseconds
      digitalWrite(2, HIGH);  // set EDIT/VPP HIGH

      if (digitalRead(53) == 1 && digitalRead(51) == 1) {  // read SDOUTA and SDOUTB
        Serial.println("EPM7032S Initialization OK");
      } else {
        Serial.println("EPM7032S - no response");
        Serial.println("Verify connections to PLD chip");
        Serial.println("End");
        return;
      }

      delay(200);    // delay 200 miliseconds
      PORTC = 0x00;  // set SS,SCK,SK,SDINA,SDINB LOW
      PORTA = 0x3B;  // set Address 0x3B (A0 to A6 pins)
      delay(50);     // delay 50 miliseconds

      eraseEPM7032();

      count = count + 1;
      Serial.print("Erase count: ");
      Serial.println(count);
      Serial.println("End");
    }
    delay(50);             // delay 50 miliseconds
    PORTA = 0x00;          // SET all pins to LOW
    PORTC = 0x00;          // SET all pins to LOW
    PORTL = 0x00;          // SET all pins to LOW
    digitalWrite(2, LOW);  // set EDIT/VPP LOW
    delay(500);
  }
}

EPM7032S eraser - first sequence :
2470101-2



EPM7032S eraser - erase sequence :
2470091-3


Arduino MEGA ports:
2470105-4
« Last Edit: December 26, 2024, 02:20:06 am by jgustavoam »
 
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