| Electronics > FPGA |
| Programming (non-JTAG) MAX7000 devices |
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| jgustavoam:
EPM7032S - controlling JTAG support bit. I'm first studying how to program the EPM7032S, and then trying to find out something about the EPM7032. I learned how to program the EPM7032S with this guy. I am very grateful to him for his didactic guidance. I will test it as soon as my JTAG chips arrive. https://youtu.be/1-oK0y2VH0Y?si=RiLJZ_ABhpBM2Yfm https://github.com/marekl123/ezPLA-VHDL I installed the Quartus II 64 bit - Version 13.0.1 program on my Windows 10 PC. https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html To enable the JTAG support bit, go to the Assignments / Device window and then click on Device and Pin Options. I think that's it. |
| jgustavoam:
EPM7032S - Do I really need 12V to program? I don't think so. http://www.pldworld.com/_altera/html/toolman/cic.org.tw-alteratutorial.htm MAX 7000S ISP • MAX 7000S devices can be programmed through 4-pin JTAG interface – By downloading the information via automatic test equipment, embedded processors, or Altera BitBlaster/ByteBlaster download cable • MAX 7000S internally generates 12.0-V programming voltage • Refer to Altera’s Application Brief & Application Note for details – AB145 : Designing for In-System Programmability in MAX 7000S Devices – AN039: JTAG Boundary-Scan Testing in Altera Devices - AN100 In-System Programmability Guidelines - AN095 In-System Programmability |
| jgustavoam:
Trying to understand the structure of an EPM7032 and EPM7064. "Note: the 7032 only has SCOA/SCOB, where as the 7064 has SCOA/B/C and D." EPM7032 has 2 LABs. EPM7064 has 4 LABs Logic Array Blocks: The MAX 7000 device architecture is based on the linking of high performance,flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays.Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions ■ Direct input paths from I/O pins to the registers that are used for fast setup times for MAX 7000E and MAX 7000S devices |
| jgustavoam:
EPM7032S programming As I already mentioned, I am learning to use the EPM7032S first and then moving on to studying the EPM7032. The internal structures are similar. I bought two used EPM7032SL44-10 chips. And an Altera USB Blaster clone module to program the chips. USB Blaster Clone with CH552 chip: https://www.eevblog.com/forum/fpga/usb-blaster-(ftdi245-vs-ch552x)-quartus-no-hardware/ Using Quartus 13.0 sp1 (32-bit) on an Intel Celeron PC / MB PCWare / Windows 7 (32-bit). https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html I used a 32-bit PC so that the environment would be as close to the reality of the 90s as possible. My PC has a parallel printer port (LPT). Using the example to program the EPM7032S: (Commodore 64 PLA replacement) https://github.com/marekl123/ezPLA-VHDL Several attempts to program both EPM7032s and neither of them were recognized. Searching in several forums and with some information from this forum, I discovered that my chips had JTAG locked. Some pins on the JTAG interface were being blocked (digital signal less than 1V) because they were configured as output and not as signal input as they should be. For example, the TDI, TMS and TCK pins. It may be a normal situation when the user intends to use the chip's JTAG interface pins in his circuit. I believe that this same behavior can appear on chips without JTAG (EPM7032), if the programming mode is not activated. Following the tips from this forum and others, I connected the OE1 pin (PLCC pin 44) to a 12V source using an 1K ohm resistor in series (a brief pulse of 12V). I was able to unlock the JTAG interface of both chips with this procedure! But I am not supplying the chip with 12V during the programming procedure. MAX7000S JTAG Lock: https://www.vogons.org/viewtopic.php?t=100864 https://www.edaboard.com/threads/quartus-jtag-id-error-using-an-epm7128slc84-7-on-pldt-2-db.116711/ https://www.elektroda.com/rtvforum/topic3844129.html https://forum.system-cfg.com/viewtopic.php?t=13192 https://community.intel.com/t5/Programmable-Devices/problem-programming-old-cpld-epm7032/td-p/156760 In the Quartus program, using the tool - JTAG Chain debugger, I can identify the chips as EPM7032S. (JTAG interface is working). But, when I try to program I have received the following message: "JTAG ID CODE SPECIFIED IN JEDEC STAPL FORMAT FILE DOESN'T MATCH ANY VALID JTAG ID CODES FOR DEVICE." I did the same tests using the "Byte Blaster MV" interface (connected with parallel port LPT1) that I built on a protoboard. And the results were the same. I assume I managed to unlock the JTAG interface of the chips, but I haven't been able to erase the original programming yet. Reading numerous Altera documents, I saw that there is a procedure to erase the chip's memory. I know that using one of Altera's parallel programmers, it is possible to erase the memory. But I don't have any of those rare and very expensive devices. The research continues... If you are interested in the ISP programming of the MAX7000S, I recommend reading the attached documents. |
| jgustavoam:
EPM7032S - IDENTIFYING THE PINS To find out and confirm that my EPM7032S chips had a blocked JTAG interface, I used a procedure based on the characteristics of the CPLD chip. This procedure can also be used on other EPM7032 chips (without JTAG). Measuring the JTAG interface signals (with scope) when I tried to program the EPM7032S, I noticed that some pins had a very low voltage level (below 1V). Therefore, communication was blocked and the Quartus program could not recognize the chip. Knowing that the maximum current on each pin can vary between +25 mA or -25 mA, I built this simple circuit, which helps identify whether the pin is an input or output. Two 220 ohm resistors in series connected to GND and +5V. The test lead to be connected to each pin of the chip must be connected between the two resistors. To measure the test voltage with a voltmeter, connect its leads to the resistor connected to ground. I filled a table with numerous voltage measurements on the pins of my chips in the state with the JTAG interface locked and then unlocked (see attached file). To identify the pins, measure the voltage: INPUT = 2.5V OUTPUT LOW = 0.25 V VCC = 5 V GND = 0 V Programming circuit to be attached to USB Blaster or Master Blaster MV (parallel Port LPT): |
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