Electronics > FPGA

Programming (non-JTAG) MAX7000 devices

<< < (17/23) > >>

GTT95:
Hello,

I'm facing quite same situation.

In my EPM7128S based design I need all 84 IO pins for the expected function.

However, I need the ISP feature to be available so that I can reflash CPLD's EEPROM while it is already mounted on the target circuit.

So my question is: once flashed and JTAG pins assigned to functionnal IO, is there a way to take back control over those pins so that the chip can be reflashed? Or is a "special" (non JTAG) programmer required to "factory reset" the chip and make the JTAG specific pins usable again for reprogramming?

Thanks a lot.

marcopolo:
That's not possible, you need a LP6 ISA board + PL-MPU+ PLM7000-84 Adapter

This is the problem that many people who buy Altera CPLDs on Ebay encounter.

Perhaps you can use a FLEX10K FPGA.

Marc

GTT95:
So only by keeping the 4 JTAG pins as dedicated to the ISP function I can continue in-circuit reflashing?

My understanding is that devices from ebay may not be blank leading to the unability to in-circuit reflash through JTAG

The FLEX10K might be a good alternative. However the ratio between max user IO ant total pins is lower than MAX7000S series (only 66 IO for 100pins devices). Other drawback is a serial configuration Flash is required which adds an extra component to the design.

Beta_vulgaris:

--- Quote from: GTT95 on June 02, 2022, 07:04:00 am ---So only by keeping the 4 JTAG pins as dedicated to the ISP function I can continue in-circuit reflashing?

My understanding is that devices from ebay may not be blank leading to the unability to in-circuit reflash through JTAG

The FLEX10K might be a good alternative. However the ratio between max user IO ant total pins is lower than MAX7000S series (only 66 IO for 100pins devices). Other drawback is a serial configuration Flash is required which adds an extra component to the design.

--- End quote ---
You can use a parallel PROM, although more pins, it can be multiplexed after configuration done as user I/Os (serial PROMs still the same, but not so ubiquitous as parallel ones).

GTT95:
Are you refering to my last remark about configuring the FPGA? Was not aware it can be configured from parallel Flash. Anyway, there will still be limitation to 66 pins IO which will force selecting a higher FPGA  with more total pins.

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version