Author Topic: PWM output with Spartan 6 OSERDES2  (Read 1175 times)

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Offline NiHaoMikeTopic starter

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PWM output with Spartan 6 OSERDES2
« on: August 15, 2021, 02:17:29 pm »
Is there a good example of how to use OSERDES2 on the Spartan 6 as PWM outputs? My understanding is that it allows a higher resolution than implementing it in general purpose logic. PWM frequency target is about 15kHz.
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Online SiliconWizard

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Re: PWM output with Spartan 6 OSERDES2
« Reply #1 on: August 15, 2021, 05:06:00 pm »
Well, sure, higher resolution for a given PWM frequency is achieved using a shorter time step, so a dedicated serializer could make sense.

Note that in your case, @15 kHz => period = 66.66... us
To get an idea, to achieve 16-bit resolution, you'd need a ~1 ns resolution, so a serializer @~1 GHz.

I don't have an example at hand, but it should be straightforward. Just feed the serializer with words made of a series of 1's (which will constitute the "high" level of the output signal) and then a series of 0's. The total number of bits, times the resolution, is the PWM period.
 

Online BrianHG

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Re: PWM output with Spartan 6 OSERDES2
« Reply #2 on: August 16, 2021, 02:16:24 am »
You basically need to manually simulate a serial position when sending a fat parallel word into the serializer to get that extended 2x/4x/5x output via software.  This is simple when you use for example, a 2:1 serializer or DDR output and have an even PWM size.

Example, say I want a 65536 PWM running at 1GHz, but my FPGA logic can only handle a 500MHz counter max, I would:

Main loop_timer = 65535 -> 0 , -2 per 500MHz clock, begin

Data serilizer 2:1 source  bit 1 <= PWM_output_val > (loop_timer - 1) ;
                                    bit 0 <= PWM_output_val > (loop_timer - 0) ;

end

You can imagine using a 4:1 serializer by running the loop_timer at 250MHz, -4 per clock and extending the source bit input to source bits 3,2,1,0.

Or you can do a 8:1, or 16:1 and slow down the speed of your loop_timer and it's section of code.  You should be able to use 3/10/20GHz transmitters to make an insanely precise PWM.

Odd numbers like 5:1 or 10:1 can also work, but, the compiler wont simplify out the logic gates a neatly as power of 2s.

(Oh, don't forget to latch 'PWM_output_val' once every loop around of 'loop_timer', otherwise you will get random gobble in the middle if the that reg changes at a lemon time.)

Also flip everything around to positive and add to simplify gate count.

Writing it out my way allows the same code to function on any vendor's FPGA who has a DDR output or a serializer output with a parallel input.  Only the IOBUF/OSERDES function initiation will be vendor specific.
« Last Edit: August 16, 2021, 02:31:10 am by BrianHG »
 


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