Electronics > FPGA

Python Script to Verilog RTL

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blackblade:
Can anyone give me an idea on how to implement an efficient Verilog HDL of the below Python code. I'm not asking for code or algorithm, just want someone to point to proper sources.

I have posted only that part which needs to be converted to RTL.


--- Code: ---# Constant def
ADC_SR = 1966.08e6
ADC_SAMPLE_SIZE = 65536
READOUT_SIGNAL_FREQUENCY = 1e6

# Data loading, the data is an array of signed short with size 65536
with open(FPATH / "sig", "rb") as r:
    sig = np.frombuffer(r.read(), dtype="i2", count=ADC_SAMPLE_SIZE)

# Processing the zero state
I = 0
Q = 0

# We iterate over the ADC signal data and multiply it with a cosine/sine wave of the same frequency
for i in range(ADC_SAMPLE_SIZE):
    t = i / ADC_SR

    # Then, we sum the results respectively
    I += sig[i] * np.cos(2 * np.pi * READOUT_SIGNAL_FREQUENCY * t)
    Q += sig[i] * np.sin(2 * np.pi * READOUT_SIGNAL_FREQUENCY * t)

--- End code ---

I have the RTL block which can generate sine and cosine wave. I'm looking more at the addition and multiplication in for loop block which loops for 65536 times. Seems like an integration to me which can be implemented in some way in Verilog.

Thanks.

agehall:
I would say that https://www.chipverify.com/systemverilog/systemverilog-tutorial contains most of the information you would need.

hamster_nz:
You would need to restructure it a little... to something like this (in no particular HDL)


--- Code: ---inputs: data_in and data_in_enable

outputs data_out_i, data_out_q and data_out_enable

on the clock edge
    if data_in_enable {
        if count == count_max {
            data_out_enable = true
            count = 0
            data_out_i = i + data_in * cos_table[count]
            data_out_q = q + data_in * sin_table[count]
            q = 0
            i = 0
        } else {
            i = data_in * cos_table[count]
            q = data_in * sin_table[count]
            count = count + 1
           data_out_enable = false
        }
    } else {
        data_out_enable = false
    }

--- End code ---

You might need to replace cos_table and sin_table  that actually calculates the required values.. (e.g. a NCO driving a CORDIC SIN+COS or a lookup table with interpolation)

Someone:

--- Quote from: blackblade on June 30, 2022, 06:51:27 am ---implement an efficient Verilog HDL of the below Python code.
--- End quote ---
Verilog (or other HDL) is just a language, it can run pretty much as you wrote it:


--- Code: ---module blackblade;

real ADC_SR = 1966.08e6;
real READOUT_SIGNAL_FREQUENCY = 1e6;
real pi = 3.141592653589793238462643383279502884197169399375;
integer ADC_SAMPLE_SIZE = 65536;
integer i;

real I = 0.0;

initial begin
    for (i=0;i<ADC_SAMPLE_SIZE;i++) begin
        I += $sin(2.0 * pi * READOUT_SIGNAL_FREQUENCY * i/ADC_SR);
    end
    $finish;
end
endmodule
--- End code ---

The code is not the hard part. How it interfaces with other things, what the target hardware is, what the system constraints/specifications are, etc etc all those details are needed to write what you actually need.

laugensalm:
There are various Python HDL approaches that would do the job, but before you dive into that you'd have to get familiar with hardware development methods and you'll have to rewrite your model in a specific HDL style. Your case is one of those typical HLS (high level synthesis) scenarios, where you have a software based model ready, and the next step would be to bake it into hardware. But that's not trivial, and the tools can't just guess and infer the right hardware accelerator for your code snippet. You'll have to deal with pipelines, how to unroll a `for ..` loop, choose the proper fixpoint arithmetics, etc. Once you've got a clocked 'true' hardware model ready though, Python can be very much your friend to verify the hardware behaviour against your software model and in general help to get things under control, down to verification of the synthesized results.

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