Electronics > FPGA
Qmtech Artix 7 Wukong board
djrm:
Greetings everyone,
This is my first post although I have been a member for a while now. I have one of the Qmtech Wukong boards and whilst learning about it I have been creating a git repo containing some support files. of interest may be the board definition files, ddr3 memory and gigabit ethernet components I have been experimenting with. Everything is briefly described here with links to the files in the readme. Its mainly Verilog and built with Vivado, I'll be adding accompanying Vitis projects shortly.
I would be interested to hear from anybody who has used one of these boards.
https://github.com/DavidJRichards/QMTECH_XC7A100T_Wukong_Board
hth David.
radiolistener:
Don't know about Xilinx boards from QMTECH, but Altera boards have some issues. For example GMII PHY clock signals are connected to a usual GPIO pins (not CLK), which prevents to use it to clock PLL for clock generation. Also they don't have CLK inputs, the only CLK input which is used is onboard 50 MHz osclillator, so you will be unable to clock your design from any other source, because Altera PLL can be clocked from CLK pins only.
djrm:
--- Quote from: radiolistener on August 01, 2021, 08:34:14 am ---Don't know about Xilinx boards from QMTECH, but Altera boards have some issues. For example GMII PHY clock signals are connected to a usual GPIO pins (not CLK), which prevents to use it to clock PLL for clock generation. Also they don't have CLK inputs, the only CLK input which is used is onboard 50 MHz osclillator, so you will be unable to clock your design from any other source, because Altera PLL can be clocked from CLK pins only.
--- End quote ---
Hi radiolistner,
Thanks, I'll have to check which pins are clock inputs, do you have a link/model for the Altera board with this problem, I'd like to compare the schematic with my own board.
I have a problem already with the qspi flash where I can't synthesize the design with the pin it is using for its clock. I have yet to test any IP using the qspi. Vitis is able to write to it though. I am looking for a PL design example to test the qspi flash.
Kind regards, David.
SiliconWizard:
I have used a few QMTECH boards with XIlinx parts, but not this one. They are OK for prototyping stuff, but all my boards have "smaller" FPGAs.
What I've read about those boards with Artix 7 100T/200T is that decoupling, and power supplies, are undersized. Not too mention no heatsink. So forget about using them using a significant fraction of the internal resources at high frequencies.
djrm:
--- Quote from: SiliconWizard on August 01, 2021, 07:39:56 pm ---I have used a few QMTECH boards with XIlinx parts, but not this one. They are OK for prototyping stuff, but all my boards have "smaller" FPGAs.
What I've read about those boards with Artix 7 100T/200T is that decoupling, and power supplies, are undersized. Not too mention no heatsink. So forget about using them using a significant fraction of the internal resources at high frequencies.
--- End quote ---
Greetings SiliconWizard, thanks for your comments.
I do not know what you have read about these boards but I see no sign of any heat sinks on any of the other entry level development boards from the major manufacturers. For my purpose which is learning about these devices the board appears quite suitable, especially considering the cost compared to the alternatives.
I shall probably find out if the decoupling is insufficient but I haven't had any stability or heat problems - I like to leave it running for a day or two from time to time to check from time to time. I imagine extra decoupling cant be retro fitted in a meaningful way.
Some other Altera boards I have bought have had loads of small peripherals onboard, eventually these become a hinderance taking up valuable pins which are more usefully exposed for other purposes, I like the mix on this board with just the high speed components on board together with a big expansion port.
Kind regards, David.
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