I am trying to use the Quartus ALTFP_SQRT IP in simulation, but the output always results in undefined state. It should take and output single precision floating point number (23 bits for mantissa, 8 for exponent and 1 for sign). Left the latency to the default value of 28 cycles and avoided any optional inputs and outputs. Clock is set to 100MHz. All files, including the generated IP .vhd, compiles without any issues. Tried feeding the input in different ways - just a constant vector, signals from other parts of the design, but output remains undefined anyways. Quartus can also compile it and generate a netlist for it, but have not tried to check in in real life yet, before I can deal with the simulation. What could be the cause for the undefined output?? Am I completely missing something??
EDIT: My personal thought is that it may be something related to the Modelsim libraries and the file describing the IP behavior is not present and it does not know how to simulate it, but I would assume that the compiler would cry about this, and I'm not really sure how to verify this.
FINAL UPDATE:
Got it working.. Initially I assumed that the behavior of the generated IP component is already present in the "altera_mf" library, which was a faulty assumption because when I started digging through the library, could not find the component, which was used in the generated ip .vhd file. What I failed to notice initially was that there were additional simulation files generated, that had to be compiled and added to the testbench. After switching to these files, dealing with some other minor compilation nonsense, simulation worked, and provided valid results (square root of 4 is indeed 2)
Thanks for the suggestions in advance!