Hello, I’m programming in Verilog under Quartus-II. My application needs a half-frequency clock, which I’m implementing as follows:
reg wrtcyc ;
always @ (clk) wrtcyc <= ~wrtcyc ; // This is line 67
Synthesis brings up a the following errors:
Warning (10235): Verilog HDL Always Construct warning at Datalink.v(67): variable "wrtcyc" is read inside
the Always Construct but isn't in the Always Construct's Event Control
Warning (10755): Verilog HDL warning at Datalink.v(67): assignments to wrtcyc create a combinational loop
The register and the overall build appears to be behaving correctly. Should I be concerned about the warnings? Is there a recommended way to do this simple task?