Author Topic: QUARTUS-II/Verilog: Unexpected warnings implementing simple subclock  (Read 1165 times)

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Offline AussieBruceTopic starter

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Hello,  I’m programming in Verilog under Quartus-II. My application needs a half-frequency clock, which I’m implementing as follows:

reg wrtcyc   ;
always @ (clk) wrtcyc <= ~wrtcyc ;     // This is line 67 

Synthesis brings up a the following errors:

Warning (10235): Verilog HDL Always Construct warning at Datalink.v(67): variable "wrtcyc" is read inside
   the Always Construct but isn't in the Always Construct's Event Control
Warning (10755): Verilog HDL warning at Datalink.v(67): assignments to wrtcyc create a combinational loop

The register and the overall build appears to be behaving correctly. Should I be concerned about the warnings? Is there a recommended way to do this simple task?
 

Offline kmike

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Re: QUARTUS-II/Verilog: Unexpected warnings implementing simple subclock
« Reply #1 on: January 09, 2023, 12:52:18 pm »
isn't it missing a posedge or negedge?

I mean always @ (posedge clk)
 
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Offline AussieBruceTopic starter

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Re: QUARTUS-II/Verilog: Unexpected warnings implementing simple subclock
« Reply #2 on: January 10, 2023, 12:44:40 am »
Oh dear. Way too late at night.
 


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