Electronics > FPGA

Quartus Prime (Time Quest) Difficulty Generating Report

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TeddyPython:
Hi, I'm looking to investigate the setup times for a design I have. However, despite following AN 775 as best I as I can, I am not generating any outputs from my design. Instead all I see are two Data ports which I haven't declared myself in my design...



Here is the pin planner - it shows these extra pins, but also my own data ports.



Furthermore here are my declared ports in my top level file.


--- Code: ---module bertfront(
    input clk,
    input inbitstream,
input [1:0] control, //[1] start, [0] reset
    output outbitstream,
    output reg ledstatus,
    output reg [31:0] totalbits,
    output reg [31:0] incorrectbits
    );
 
--- End code ---

Can anyone shed some light as to why I'm not seeing my own data ports in the timing analysis? If you need any more code I would be happy to share the entire project.

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