Author Topic: Quartus Prime 18.1 Can't fit design in device  (Read 476 times)

0 Members and 1 Guest are viewing this topic.

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Quartus Prime 18.1 Can't fit design in device
« on: August 07, 2020, 05:47:47 pm »
I'm trying to implement a frame buffer in the Cyclone 4 EP4CE6. The image size is 512x256 pixels, 2 bits. I made a 2 port RAM with 2 bits bus 262144 bits total memory. I compiled the project yesterday night and this morning many times and everything went well, see attached. All of sudden though, I started getting an error, in the attachment, and no matter what I do, it doesn't remember how to fit the design in this device. If I select the next device up  EP4CE10, it compiles fine and even programs and works well on EP4CE6.
Is there any trick or any setting I need to click to remind Quartus that it was able to fit this design in this device. There's plenty of RAM there. I tried Auto and M9K for memory type with no success and it is not related to the .mif file. I tried without it and still doesn't work.
« Last Edit: August 07, 2020, 08:55:35 pm by Miti »
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #1 on: August 07, 2020, 05:58:40 pm »
Please show us the compiler report's device utilization section following these tabs:

Fitter - Resource Section - Ram Summary

Then do a ctrl-A to select all the text and do a CTRL-C to copy that text and then paste into this forum under 'CODE' so we should see something like this:

Code: [Select]
vid_osd_generator:inst9|palette_mixer:pmixer|sixteen_port_gpu_ram:palette_RAM|gpu_quad_port_ram:gpu_RAM|gpu_dual_port_ram_INTEL:dual_port|altsyncram:altsyncram_component|altsyncram_3qk2:auto_generated|ALTSYNCRAM AUTO True Dual Port Single Clock 512 16 512 16 yes yes yes yes 8192 512 16 512 16 8192 1 palette.mif Unassigned Don't care Old data Old data Off No Yes 1
vid_osd_generator:inst9|sixteen_port_gpu_ram:gpu_RAM|gpu_quad_port_ram:gpu_RAM|gpu_dual_port_ram_INTEL:dual_port|altsyncram:altsyncram_component|altsyncram_apl2:auto_generated|ALTSYNCRAM                       AUTO True Dual Port Single Clock 24576 16 24576 16 yes yes yes yes 393216 24576 16 24576 16 393216 48 GPU_MIF_CE10_10M.mif Unassigned Don't care Old data Old data Off No Yes 2
« Last Edit: August 07, 2020, 06:02:47 pm by BrianHG »
__________
BrianHG.
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #2 on: August 07, 2020, 06:23:11 pm »
Ooops, my bad, 512x256x2 = does equal 262144.  The device divides memory into M9K blocks which are 8 bit or 9 bit wide depending on your design implementation meaning that for 2 bit ram, you take 262144/8192 to get the number of M9K blocks which means you need 32 x M9K blocks space on the FPGA to make your ram.

The EP4CE6 only has 30 x M9K blocks in total.

If you want a scan doubler on a EP4CE6, you will need to do it with a ram which has the memory for few lines of video instead of storing a complete frame.

Unless you are willing to make some code to take advantage of that 9th bit in the M9K memory blocks meaning instead of 262144x2 ram, you make a 30720x9 ram (276480 bits of ram) and stuff/pack your source video in and out along that 9 bit wide bus using some 9/8 - 8/9 arithmetic to generate an address an which bits to use.  This will be a headache, but it is possible.


Now, are you sure your Y is 256?  If it is actually 240, then that's 30 x MK9 blocks of ram exactly.  This you can do.
« Last Edit: August 07, 2020, 06:27:52 pm by BrianHG »
__________
BrianHG.
 

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #3 on: August 07, 2020, 06:26:43 pm »
Here it is:

Code: [Select]
Img_RAM:Img_RAM|altsyncram:altsyncram_component|altsyncram_t9n1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 131072 2 131072 2 yes no yes yes 262144 131072 2 131072 2 262144 32 ./VGA_Controller/HP8590.mif Unassigned Don't care New data with NBE Read New data with NBE Read Off No Yes 1
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #4 on: August 07, 2020, 06:29:54 pm »
Now, are you sure your Y is 256?  If it is actually 240, then that's 30 x MK9 blocks of ram exactly.  This you can do.

512*240*2 = 245750 / 8192 = 30 MK9 blocks.

Read the number after here:
262144   32   ./VGA_Controller/HP8590.mif

32 = 32 M9K blocks of ram.
262144 bits / 8192 = 32.
« Last Edit: August 07, 2020, 06:33:23 pm by BrianHG »
__________
BrianHG.
 

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #5 on: August 07, 2020, 06:45:26 pm »
But it worked before and it still works with EP4CE6 if I compile for EP4CE10...
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #6 on: August 07, 2020, 06:59:09 pm »
Was the memory originally wired to something.  If the ram is placed in the design, yet not doing anything, the compiler will simplify it out.  For example, even if a single address line was always a '0' or '1' because of logic feeding the ram's address input, the compiler would automatically cut your memory in half since half of the ram wouldn't ever be addressed.

If you only wired 1 of the output bits, or if 1 of those wired output bits was ignored due to logic, again the compiler would cut your ram in half, basically turning it into 1 bit ram since it half was never read.

Yes, FPGA compilers are that aggressive in automatically saving resources.

EP4CE10 has a crap load more memory than the EP4CE6.
Remember, you are only 2 blocks shy of fitting the design into a EP4CE6.  Or, 16 lines less of picture will also fit into an EP4CE6.

If earlier, you only wired 1 bit of ram to generate that image, the compiler simplified the ram down to 16 blocks, or 1 bit wide, IE half the ram size.

If you didn't wire the ram output to anything, then the compiler would have ignored the ram when building the FPGA.

It's not like a C compiler where you allocate ram.  The FPGA compiler thinks and see if parts of your design actually generates some sort of effect on the output pins.  If not, that portion of your design gets thrown out, completely ignored.

« Last Edit: August 07, 2020, 07:14:54 pm by BrianHG »
__________
BrianHG.
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #7 on: August 07, 2020, 07:20:15 pm »
None of this means you cannot get you project to fit into a EP4CE6, including the startup graphic.  You just need to be a little clever.  I said you can do a ram block of 512x240x2bit.  So maybe, just for your logo, just shave off 8 lines at the top and 8 lines on the bottom.  Once converting the image from the spectrum analyzer, since the V-sync is locked from in to out, just circulate around a few lines in that graphic buffer, 2-4 would be enough, though you have 240 to play with.

The nice thing about circulating 2-4 lines is that you may retain the boot graphic even during operation.

BTW, is the logo supposed to look squished like that?
« Last Edit: August 07, 2020, 07:23:29 pm by BrianHG »
__________
BrianHG.
 

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #8 on: August 07, 2020, 07:30:48 pm »

If you only wired 1 of the output bits, or if 1 of those wired output bits was ignored due to logic, again the compiler would cut your ram in half, basically turning it into 1 bit ram since it half was never read.


Man, you know your stuff! That was it, I only used bit[1] before. Once I started using bit[0] in my code, it didn't fit anymore, even though the mif file was 2 bits. I went back to one bit and it compiles again.
I have 254 visible line so I think I need the EP4CE10 if I want a full frame buffer. Which is OK, it is only few dollars more at LCSC.
Thank you sir, I learned something today!

Edit: The question still remains. How comes it works with EP4CE6 if I compile for EP4CE10? Where does it get those extra memory blocks from? Is 4CE6 a 4CE10 that failed some tests?
« Last Edit: August 07, 2020, 07:42:14 pm by Miti »
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #9 on: August 07, 2020, 07:46:35 pm »

If you only wired 1 of the output bits, or if 1 of those wired output bits was ignored due to logic, again the compiler would cut your ram in half, basically turning it into 1 bit ram since it half was never read.


Man, you know your stuff! That was it, I only used bit[1] before. Once I started using bit[0] in my code, it didn't fit anymore, even though the mif file was 2 bits. I went back to one bit and it compiles again.
I have 254 visible line so I think I need the EP4CE10 if I want a full frame buffer. Which is OK, it is only few dollars more at LCSC.
Thank you sir, I learned something today!
Well, with a full buffer and a second generation FTDI USB chip with their high speed 8bit parallel bus, you can send a second live 60fps video to the PC as a second monitor & do screen snapshots.

If you want, you can use some additional FPGA IOs and a logic IC or 2 to trick the analyzer's panel buttons, you can then add a remote panel control on the PC through your viewing software making the analyzer seem like a brand new modern integrated lab tools.  BTW, for a real-time 60FPS video of your scope buffer, you need a 20 megabit link, or 2 megabytes per second.  Some WiFi modules can even do that.
« Last Edit: August 07, 2020, 08:04:11 pm by BrianHG »
__________
BrianHG.
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #10 on: August 07, 2020, 08:02:36 pm »
Edit: The question still remains. How comes it works with EP4CE6 if I compile for EP4CE10? Where does it get those extra memory blocks from? Is 4CE6 a 4CE10 that failed some tests?

 :-//  What are you trying to say?   :-/O

Did you select in Quartus the FPGA 4CE10, compile and then programmed that build into your 4CE6 on your PCB?
I could not imagine this working at all.
These arent microcontrollers with just a larger ram section on the die where it is just addressed as a larger block of ram.
I would expect the board just not to boot up at all.

(Wouldn't it be nasty of Altera that the first 2 Cyclones all have the same die and just a different fuse programmed JTAG bit.  I cant imagine the larger ones which have a massively larger amount of ram & gates and multipliers actually being the same of the bottom tier devices.  Also cant guarantee full speed or all bits and logic functional.)
« Last Edit: August 07, 2020, 08:22:54 pm by BrianHG »
__________
BrianHG.
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #11 on: August 07, 2020, 08:19:17 pm »
LoL, take a look at this Cyclone III and Cyclone IV datasheet comparison.  The Cyclone IV CE series is virtually identical to the Cyclone III, except for maybe a few swapped IO pins.  But look at the memory bits of the first 2 devices in each Cyclone type.  I wonder if Altera artificially lowered the bit size of the 4CE6, as you can see in the device selection tables.

[attachimg=1]

Both devices are so small that Altera may have abandoned the 4CE6 and just a laser burned fuse or 2 difference between that and the 4CE10.  I think that JTAG may see the difference and stop you, but AS active serial may not see device ID bits.
« Last Edit: August 07, 2020, 08:30:14 pm by BrianHG »
__________
BrianHG.
 

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #12 on: August 07, 2020, 08:54:15 pm »
Edit: The question still remains. How comes it works with EP4CE6 if I compile for EP4CE10? Where does it get those extra memory blocks from? Is 4CE6 a 4CE10 that failed some tests?

 :-//  What are you trying to say?   :-/O

Did you select in Quartus the FPGA 4CE10, compile and then programmed that build into your 4CE6 on your PCB?
I could not imagine this working at all.
These arent microcontrollers with just a larger ram section on the die where it is just addressed as a larger block of ram.
I would expect the board just not to boot up at all.

(Wouldn't it be nasty of Altera that the first 2 Cyclones all have the same die and just a different fuse programmed JTAG bit.  I cant imagine the larger ones which have a massively larger amount of ram & gates and multipliers actually being the same of the bottom tier devices.  Also cant guarantee full speed or all bits and logic functional.)

Yeap, and here is the proof. Two bits of color, full frame. I didn't post the full frame because I don't want HP to come after me for using their logo. 00 gives red, 01 gives green and 11 gives blue. I program in JTAG mode and the device in the programmer is EP4CE10E22. The board has EP4CE6E22 and comes from Aliexpress. Supplies!!
« Last Edit: August 07, 2020, 09:00:38 pm by Miti »
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #13 on: August 07, 2020, 09:04:19 pm »
You are not using HP's logo to sell your own hardware.  This means using the HP logo here on the forum as a test is ok, but, selling your device with an embedded HP logo can be interpreted as if you were HP themselves marketing this add on/upgrade device for their spectrum analyzers which you created.  That is a big red no-no unless it is absolutely clear you are demonstrating a new monitor hooked up the the analyzer and that HP logo was actually generated in the analyzer which your hardware was just passing through.

Otherwise I would be in trouble for all the .pdf screenshots I post here.

Now, you may make a clear caveat with all your posts that this HP logo is trademarked by HP and you are not in any business relations with them in any way.
« Last Edit: August 07, 2020, 09:08:19 pm by BrianHG »
__________
BrianHG.
 

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #14 on: August 07, 2020, 09:24:39 pm »
You are not using HP's logo to sell your own hardware.  This means using the HP logo here on the forum as a test is ok, but, selling your device with an embedded HP logo can be interpreted as if you were HP themselves marketing this add on/upgrade device for their spectrum analyzers which you created.  That is a big red no-no unless it is absolutely clear you are demonstrating a new monitor hooked up the the analyzer and that HP logo was actually generated in the analyzer which your hardware was just passing through.

Otherwise I would be in trouble for all the .pdf screenshots I post here.

Now, you may make a clear caveat with all your posts that this HP logo is trademarked by HP and you are not in any business relations with them in any way.

I was more worried about modifying the logo rather than the logo itself. Using a screen shot with a logo in some test instructions, for example, that says this is what you should see when you power up this device is ok, changing the color of that logo and stretching it vertically or horizontally is not.
Anyway, here is my test pattern with 4 colors, if white and black can be considered colors. Four combinations of colors, full frame. Just to prove that compiling on 4CE10 and loading it in 4CE6 works. Hmm, or does it? Is my device a fake, rejected, re-lasered EP4CE10?
That big spark at power up was by design!
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 4488
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #15 on: August 07, 2020, 09:33:38 pm »
If you connect in JTAG mode, the device ID will say which Cyclone it is.
As for my datasheet link above, you can see the the 2 bottom Cyclone III have the 414kb ram, just the logic gate size is different.

I do not think what you are doing would work unless the 2 Cyclone IV dies are identical and the price difference is just a means of making more profit from the same device being mass produced.

As soon as you go to the Cyclone IV 4CE15, I doubt this will work.  Even a few IOs are different, but, if this is done just during the die bonding in the 144pqfp package, maybe a simple design might work less those IOs.

« Last Edit: August 07, 2020, 09:38:30 pm by BrianHG »
__________
BrianHG.
 

Offline Someone

  • Super Contributor
  • ***
  • Posts: 2518
  • Country: au
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #16 on: August 07, 2020, 11:36:31 pm »
I do not think what you are doing would work unless the 2 Cyclone IV dies are identical and the price difference is just a means of making more profit from the same device being mass produced.
Altera and Xilinx both do this across most of their product lines (even the mid and high end parts). I've not seen more than adjacent parts from Altera sharing a die, but Xiinx have some larger spans of 3 device sizes:
https://www.eevblog.com/forum/fpga/are-xilinx-xc7a35t-actually-the-same-die-as-something-else-or/?all
https://www.eevblog.com/forum/microcontrollers/artix-7-only-has-three-different-die-sizes/msg833861/
looking at the regions that are "locked off" its not just a simple % of the device so there is some yield aware restrictions. But as to whether they are tested individually, or if the smaller parts are known to have failed is up in the air (could just as likely be they are 100% fine, especially later in production).
 
The following users thanked this post: Miti, BrianHG

Online Miti

  • Frequent Contributor
  • **
  • Posts: 837
  • Country: ca
Re: Quartus Prime 18.1 Can't fit design in device
« Reply #17 on: August 08, 2020, 01:03:56 am »
If you connect in JTAG mode, the device ID will say which Cyclone it is.
As for my datasheet link above, you can see the the 2 bottom Cyclone III have the 414kb ram, just the logic gate size is different.

I do not think what you are doing would work unless the 2 Cyclone IV dies are identical and the price difference is just a means of making more profit from the same device being mass produced.

As soon as you go to the Cyclone IV 4CE15, I doubt this will work.  Even a few IOs are different, but, if this is done just during the die bonding in the 144pqfp package, maybe a simple design might work less those IOs.

Check this out, looks like it cannot distinguish between a broad range of devices. How do you read the device ID?

And indeed, it doesn't work with 4CE15 and 4CE22.
That big spark at power up was by design!
 
The following users thanked this post: BrianHG


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf