Electronics > FPGA

Question about shortest-path algorithm during synchronous circuit synthesis

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promach:
In Retiming synchronous circuitry , why put a negative sign to d(u) in step 1 ? Why there is no subtraction operation for W(u, v) in step 3 ?

Note:

1. The quantity W(u, v) is the minimum number of registers on any path from vertex u to vertex v
2. The quantity D(u, v) is the maximum total propagation delay on any critical path from u to v

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