Electronics > FPGA

Questions on USB protocol

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promach:
From https://www.keil.com/pack/doc/mw/USB/html/_u_s_b__protocol.html and https://github.com/sigrokproject/sigrok-dumps/tree/master/usb/setup , I have few questions:

1. Why there are two different pipes labelled as 1 and 2 ?

2. What does it mean by 8 microframes of 125us ?

3. Why the usb_failed_setup_fullspeed.sr waveform being a failed setup ?

4. I do not quite understand the dribble mechanism in section 7.1.9.1 of usb2.0 specification document.







ataradov:
1. It just shows that in a single frame there may be communication with multiple devices or sub-devices withing the same device. From the host perspective they are pipes. From the device - endpoints.
2. In HS planing intervals (frames) are 8 times shorter and are called micro-frames. It does not change much as far as actual operation goes, 1 ms was just too long for high speeds.
3. Edited my response. It is incorrect. Let me figure out what is actually going on. It still looks like there was a STALL response at some point, but it is not shown here.
4. No idea if this will ever happen in practice with modern hardware. This was written in times when HS did not exist and hubs could have slow single-ended switches that could distort the signal when switching from differential to single-ended mode.

promach:
4.  What do you exactly mean by hubs could have slow single-ended switches that could distort the signal when switching from differential to single-ended mode. ?

ataradov:
Normal communication is differential - D+ and D- switch at the same time. The bit value is determined by the difference. When EOP is signaled, both lines go low. Which means that one of the lines has to stay low, and the other one will have to switch from high to low. This transition from differential to single ended mode may change bit timings.

Again, this has not been a problem for 20+ years in real life, this is just a leftover from very early days of the standard, but they can't just remove things.

promach:
2.  Check section 8.4.3.1 USB Frames and Microframes inside USB 2.0 specification.

Could you comment a bit more about 5.9 High-Speed, High Bandwidth Endpoints with regards to the microframe ?


--- Quote ---USB supports individual high-speed interrupt or isochronous endpoints that require data rates up to
192 Mb/s (i.e., 3072 data bytes per microframe). One, two, or three high-speed transactions are allowed in
a single microframe to support high-bandwidth endpoints.
--- End quote ---

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