Basic Clock and PLL Question -- reading datasheets

[TheGreatNed]

Hello good FPGA people,

I have a Cyclone 4 dev kit with a 50MHz default clock as defined in the .sdc file. I'm using a PLL IP block to get a 125MHz output. Question 1: Can I simply feed this clock to my design instead of the 50mhz one and expect all the registers to work normally? (basically free speed?)

I'm wondering how fast I can go based on the below datasheets (I'm using a EP4CGX150 with speed grade 'C7')



^This datasheet seems to say I can use the embedded multiplier and memory blocks at up to 437.5MHz (without consequence?)... but what about the everyday gates/registers/LUTs?



^This datasheet seems to say that the input to any PLL can be <=450MHz, and the output "to global clock" can also be <=450mhz. What things do i need to consider if i dial up my core clock right to 450mhz via a pll?

Thanks

[hamster_nz]

Your timing report will tell you if your logic is too complex for the desired clock rate.  If you have correctly constrained your incoming clock to 20 ns, the tools will usually work out all derived timing constraints (8 ns for the 125MHz logic).

Datasheet timing show the performance of the individual resources (FFs/LUTs/PLL...), and not the performance of the overall system built from those resources. You will have the timing requirements of the resources, plus additional 'routing' delays due to the connections between parts.

125MHz isn't that fast for a Cycleon IV FPGA - It will most likely work OK unless it has lots of logic.

[TheGreatNed]

So what does the 437.5mhz number mean exactly in the above datasheet?

Do I need to add an entry in my SDC file telling quartus about my 125mhz PLL and where its going?

[NorthGuy]

So what does the 437.5mhz number mean exactly in the above datasheet?

It means that if you feed a clock signal above 437.5 MHz to the clock distribution system, they cannot guarantee that the clock distribution system will work on every device even if the voltage and temperature are within the specified range.

Besides the clock distribution system, there are are things inside FPGA which have their own timing characteristics. You need to make sure that your design doesn't violate any of them. Generally, it is difficult to design something that works at the highest clock frequency. Designing for 200 MHz clock is easier.

[TheGreatNed]

Awesome, thank you 

it seems that "derive_pll_clocks" is all that is required in the SDC file to inform the compiler of my 125mhz clock. Easy enough