problem with AXI bus

[e0ne199]

Hello everyone, i have a problem with sending data over AXI bus. The data I want to send is an array of int (392 row and 30 column), but when I try to send it with AXI stream, the AXI stream throws an error...do you know what to do in this situation? any response is really appreciated, thx before.

[Someone]

but when I try to send it with AXI stream, the AXI stream throws an error...

Which error?
You will need to share many more details to get help/advice.
An AXI Stream endpoint/sink provides no status/error/reporting, it is either accepting data or it is not.

[e0ne199]

but when I try to send it with AXI stream, the AXI stream throws an error...

Which error?
You will need to share many more details to get help/advice.
An AXI Stream endpoint/sink provides no status/error/reporting, it is either accepting data or it is not.

hello, this is my way of sending the matrices to AXI stream, let me know if you need more details :

Code: [Select]

*(accelCtrl+0) = 0x00000002;
	xil_printf("slv_reg0 mat A2: 0x%08x\n\r", *(accelCtrl+0));


	// DMA transfers matrix A2 to the accelerator
	status = XAxiDma_SimpleTransfer(&AxiDma,(int) weights_layer1_part2, layer_part_1_size, XAXIDMA_DMA_TO_DEVICE);

	if (status != XST_SUCCESS) {
	    xil_printf("Error: DMA transfer matrix A2 to accelerator failed\n");
	    return XST_FAILURE;
	}

	// Wait for transfer of matrix A2
    while (XAxiDma_Busy(&AxiDma, XAXIDMA_DMA_TO_DEVICE)) ;

I am able to send arrays of int with size 30x10 to the AXI stream but unable to do so when I try to send arrays larger than that...is there anything that I have to configure on the PL side?

[Siwastaja]

If

Code: [Select]

if (status != XST_SUCCESS)

is failing, then the obvious thing to do is to print the value of status and compare it to the documentation of XAxiDma_SimpleTransfer(), which can be found with 5 seconds of Googling:
https://xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b

Code: [Select]

Returns

        XST_SUCCESS for success of submission
        XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going
        XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in

[e0ne199]

If

Code: [Select]

if (status != XST_SUCCESS)

is failing, then the obvious thing to do is to print the value of status and compare it to the documentation of XAxiDma_SimpleTransfer(), which can be found with 5 seconds of Googling:
https://xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b

Code: [Select]

Returns

        XST_SUCCESS for success of submission
        XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going
        XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in

yes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side?

[Someone]

Where is the AXI stream in this? The code example supplied is using some high level software to interact with a DMA engine.

yes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side?

So you want to send data to the PL, but dont have anything on the PL side? This sounds like you're just throwing stuff at a wall with no plan of how it should function.

[e0ne199]

Where is the AXI stream in this? The code example supplied is using some high level software to interact with a DMA engine.

yes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side?

So you want to send data to the PL, but dont have anything on the PL side? This sounds like you're just throwing stuff at a wall with no plan of how it should function.

I am sorry but do you want to have a look at the PL side too?

[glenenglish]

please post the waveform  from the simulator output. pre-synthesis  is a good start.
or , post the chipscope / ILA output