reading csv file for test-bench in verilog

[ali_asadzadeh]

Hi,
I have captured an SPI bus from a logic analyzer, and have saved the data in a csv file, Now I want to read the csv file in the test bench and input the data as stimulate signals to my DUT, how it should be done?

I have done a simple task of reading plain text files with only one variable like this before,

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reg [15:0] r_someData [0:1024];
file1=$fopen("smoeData.txt","r");
$fscanf(file1,"%d", r_someData [j]);
$fclose(file1);
Please note that the csv file has multiple data on a single line, also the data is repeated 2 times because of the 2X sampling clock,
How should I read multiple data from the csv file, and How should I apply the data to my DUT, because I want my DUT use exactly the i_clk and G_SCK from the input file, and I do not want to generate the clock from the code in test bench
The file is attached for your reference

[dtodorov]

Hi,

looking at the csv file, you have the format

Code: [Select]

time unit: us, i_clk, G_MISO, G_SCK, G_MOSI, G_SS.
Therefore you fscanf() should be a bit more complicated. Something like this:

Code: [Select]

for (i=0; i<2^16; i=i+1) begin
    r = $fscanf(file1,"%d, %d, %d, %d", t[i], s1[i], s2[i], s3[i] );
end
Reading from a file with $fscanf() increments the file position index, thereby repeated $fscanf calls advance in the text processing.  Depending on your CSV size, you may need to adapt the for(..) conditions.

P.S. You may also youse while(..) loop and observe the result of the $fscanf(). I have named it "r" in the example and it will return a -1 upon EOF (end of file) condition. You may also just use $feof(file..); task.

Hope that helps. 

[ali_asadzadeh]

Thanks dtodorov for the tip.