Register power consumption on FPGAs

[MichailM]

Hello everyone, recently I came up with the following question. On FPGA registers whenever there is a transition some amount of power is consumed but is that amount of power the same for 0->1 and 1->0 transitions? And what about the 0->0 and 1-> is any power consumed there?

Thanks in advance for your answers!

[ogden]

Hello everyone, recently I came up with the following question. On FPGA registers whenever there is a transition some amount of power is consumed but is that amount of power the same for 0->1 and 1->0 transitions? And what about the 0->0 and 1-> is any power consumed there?

Thanks in advance for your answers!

Here you go:

http://www.ti.com/lit/an/scaa035b/scaa035b.pdf

[MichailM]

Thanks a lot for your answer although I don't think that it is what I am looking for. My question is not about the CMOS technology in general but as how it is implemented in FPGAs and to clarify further I am interested in the artix-7 series from Xilinx.

[ogden]

Thanks a lot for your answer although I don't think that it is what I am looking for. My question is not about the CMOS technology in general but as how it is implemented in FPGAs and to clarify further I am interested in the artix-7 series from Xilinx.

No matter it is simple CMOS register or FPGA, they both have static (leakage) consumption and dynamic consumption. Principles are the same, just numbers differ.

[jmelson]

Power is consumed every time the clock is cycled, whether a FF changes state or not.  Then, depending on routing, the output goes to a number of lines that may stretch somewhat across the die.  At intervals, there are repeater buffers on the lines, which draw power when their state changes.  So, the amount of power changes depending on how much wire, repeaters and inputs are being driven.

So, the answer is it is pretty hard to give a simple NUMBER for it.  But, in general, a 0-> 1 transition will cause very similar dissipation to a 1-> 0 transition.

Jon

[hamster_nz]

Hello everyone, recently I came up with the following question. On FPGA registers whenever there is a transition some amount of power is consumed but is that amount of power the same for 0->1 and 1->0 transitions? And what about the 0->0 and 1-> is any power consumed there?

Thanks in advance for your answers!

For the power difference between 0->1 and 1->0 transitions that it is very hard to create a test case where this matters. Changing a single flip-flop to each cycle is too small and gets lost in the overall power usage. Changing a large number of flip-flops is creates only a short transient, which is also difficult to measure due to decoupling.... maybe you can think of an implementable test case?

A register not change from 0->0 and 1->1 will some consume power, because it implies a clock edge is being seen by the FF. Power will be used within the FPGA's clock distribution network to get that clock edge to the FF.

[NorthGuy]

0->1 and 1->0 should be the same.

But this shouldn't really matter in practice, because in any process both transitions occur at the rate. Otherwise, all flops would eventually migrate to either '0' or '1'.

You can try to see if you can even detect this power - link all the flops into a long shift register - fill it with '0' then apply '1' and wait until it comes out. This is your case for '0' to '1'. Then feed it with '0' and wait for it to come out. This is your '1' to '0' case. Compare the consumption. Since this is only one flop per cycle, you may not even see the difference with the reference 'no change' case. But you can make 1000 such shift registers, or 100,000. It'll produce more energy, but will make your time window much shorter.

[langwadt]

0->1 and 1->0 should be the same.

But this shouldn't really matter in practice, because in any process both transitions occur at the rate. Otherwise, all flops would eventually migrate to either '0' or '1'.

You can try to see if you can even detect this power - link all the flops into a long shift register - fill it with '0' then apply '1' and wait until it comes out. This is your case for '0' to '1'. Then feed it with '0' and wait for it to come out. This is your '1' to '0' case. Compare the consumption. Since this is only one flop per cycle, you may not even see the difference with the reference 'no change' case. But you can make 1000 such shift registers, or 100,000. It'll produce more energy, but will make your time window much shorter.

make flip flops instead and see if you can tell the difference

[SiliconWizard]

As said above: in practice, it doesn't really matter and it could be very hard to model properly. Dynamic power draw is usually expressed as a function of clock frequency, not individual edges. And if you're asking, that would mean that you're considering cases where edges would not occur symmetrically - which would equate to a decreased average frequency. You get the idea. And on most CMOS ICs that are as large as an FPGA (except maybe on extremely old processes), below a given average frequency (most often at least a few MHz or higher), static power draw will dominate anyway.

I don't think there is anything much specific to Xilinx FPGAs. To estimate the relative power consumption of registers, I would probably model it as a function of the register's clock frequency AND the average clock frequency of each individual register bit. I would expect a given register to draw less power if it doesn't change values, or if it does so slower.

Xilinx tools include a power estimator, so feel free to use it. That could also be interesting to measure that directly with some test patterns. But I'm not sure you would see anything much except that generally speaking, the more signal toggles per unit of time, and the higher the power consumption...

In many FPGAs though, due to the way clocks are distributed, the overall power consumption is a function of the clock frequency and doesn't depend that much on the design unless you're using A LOT of logic cells or specific blocks such as memory controllers.

In the same vein, clock gating to lower power consumption may not always be trivial to do properly on FGPAs (some vendors publish app notes about how to write RTL to do clock gating).

[MichailM]

Thank you everyone for your replies!
I will try to sum up the information given to make sure I have not misunderstood anything.
Transitions from 1->0 and 0->1 consume statistically the same amount of power.
Non-transitions (0->0 and 1->1) still consume power but its significantly less. This happens because there is power consumption during the clocking of the register.
To model and measure the power consumption is hard because it depends on many factors.

Also it is stated that most of the times the static power consumption dominates over the dynamic. If you make a large enough design to make the dynamic power dominant, assuming that you are using registers,luts,muxes and carry units (no brams, DSPs or anything else) will then the power consumed in the register transitions be the dominant source of power consumption?
Or something like what SiliconWizard describes here will happen so the power consumption pattern  will not have to do with the register switching activity?

In many FPGAs though, due to the way clocks are distributed, the overall power consumption is a function of the clock frequency and doesn't depend that much on the design unless you're using A LOT of logic cells or specific blocks such as memory controllers.

[NorthGuy]

Also it is stated that most of the times the static power consumption dominates over the dynamic.

Myth. In all my designs with 7-series FPGA, the dynamic power dominates. This happens long before you need a heatsink.

The power roughly depends on the frequency and resource utilization - if you run at higher frequency and consume more resources, there will be more dynamic power.

I suggest you experiment with this. Xilinx has a temperature sensor inside FPGA, so you can roughly compare power consumption of various designs without any equipment. Make sure you enable high temperature shutdown though.

[MichailM]

Also it is stated that most of the times the static power consumption dominates over the dynamic.

Myth. In all my designs with 7-series FPGA, the dynamic power dominates. This happens long before you need a heatsink.

The power roughly depends on the frequency and resource utilization - if you run at higher frequency and consume more resources, there will be more dynamic power.

I suggest you experiment with this. Xilinx has a temperature sensor inside FPGA, so you can roughly compare power consumption of various designs without any equipment. Make sure you enable high temperature shutdown though.

Thanks for your reply!
The grand majority of that dynamic power will be spend on the transitions of the registers, right?

[SiliconWizard]

On the transitions of all transistors that are switching. That's a lot more than just the registers.

[MichailM]

On the transitions of all transistors that are switching. That's a lot more than just the registers.

So the registers will still not be the dominant power consumption source. Can you give examples of other elements with switching activity and how their energy consumption compare to that of the registers?

[ogden]

So the registers will still not be the dominant power consumption source.

In case your design is dominated by registers, they indeed will be dominant power consumption source in FPGA. You make sure you understand basics of FPGA logic block power consumption which were already explained, then just use FPGA power estimation software.