Replicating a 'custom' 6800 in FPGA

[metertech58761]

So, I have this project that I built just to say I built it - a copy of an obscure bit of test equipment from the mid '80s.

Thing is, it uses a CPU that is an industrial 6800 variant (more precisely, it has the 6801 instruction set, yet the pinout is similar to a stock 6800).

It seems the chip I salvaged turned out to be dead... and the only place that even has any left quoted me a price over $50 apiece.

So, I'm curious if anyone has made an FPGA adapter for a 6800-class MPU?

[rstofer]

I haven't counted the pins but maybe the Digilent CMOD S6 or A7 can do the job.  I suspect there will need to be a carrier board between the project board and the CMOD to straighten out some signal pinouts.

https://digilent.com/shop/boards-and-components/system-boards/cmods/

There's a MC6803/6801 core at OpenCores.org if you need one.

[joeqsmith]

Do you have the project documented somewhere (schematics, source, layout...)?       

[james_s]

There is a 6800 core that I've used in some projects, although it is not cycle accurate, I don't know if that matters to you or not. It is certainly possible to use a FPGA soft core interfaced to original hardware but I don't know if there is a ready to go core that will do exactly what you want.

[rstofer]

Voltage levels may be a problem.

[BrianHG]

You would need to edit the core to drive the 'OE' and 'DIR' of a bunch of on-circuit 3.3v powered 74LVC245 to support 5v TTL safely.

[langwadt]

You would need to edit the core to drive the 'OE' and 'DIR' of a bunch of on-circuit 3.3v powered 74LVC245 to support 5v TTL safely.

Voh of 3.3V is well within the minimum Vih of 5V TTL

[BrianHG]

You would need to edit the core to drive the 'OE' and 'DIR' of a bunch of on-circuit 3.3v powered 74LVC245 to support 5v TTL safely.

Voh of 3.3V is well within the minimum Vih of 5V TTL

On Nockieboy's 8bit GPU thread, we had no problem using the 74LVC245 interfacing with a Z80 bus which contained the Z80 plus numerous additional 5v TTL peripherals.  I guess if you wanted additional margin, you could power the 245s with 3.8v hitting the maximum a 3.3v FPGA inputs can safely tolerate gaining an additional .5v on your high outputs.

[langwadt]

You would need to edit the core to drive the 'OE' and 'DIR' of a bunch of on-circuit 3.3v powered 74LVC245 to support 5v TTL safely.

Voh of 3.3V is well within the minimum Vih of 5V TTL

On Nockieboy's 8bit GPU thread, we had no problem using the 74LVC245 interfacing with a Z80 bus which contained the Z80 plus numerous additional 5v TTL peripherals.  I guess if you wanted additional margin, you could power the 245s with 3.8v hitting the maximum a 3.3v FPGA inputs can safely tolerate gaining an additional .5v on your high outputs.

Vih for TTL is only 2.4V, so 3.3V CMOS will easily drive that, so that is safe

Voh for standard TTL is quite wimpy, hence the low threshold, but relying on that not overdriving a 3.3V input is sketchy at best

[metertech58761]

Oh my. Didn't expect to see so many replies this quickly.

Going through the replies:

I did see the 6801 / 6803 listing at OpenCores...

I was figuring that I'd likely need to work out a carrier board to be able to drop the FPGA into the circuit.

I do have schematics of what I started with - can make a PDF of the whole thing and attach it a bit later on.

As long as whatever core is used works with a 1MHz clock and the NMI handling works well, I'll be happy.

Good to know that level-shifting will be needed - are ALL FPGAs 3.3V only, or are there any that are 5V-tolerant?

[james_s]

To my knowledge there are no modern FPGAs that are 5V tolerant although older ones certainly exist and you may still be able to source one. Whether it's worth trying to use an old part (and the old software required to work with it) vs just using level shifters is something you'll have to decide.

[woofy]

I've discovered the ice40 HX8k appears to be 5v tolerant, at your own risk though. Lattice says 3.3v.
https://www.eevblog.com/forum/fpga/ice40-hx-a-5v-tolerant-fpga/msg3580451/#msg3580451
I have a project running feeding 5v PS2 keyboard signals into and HX8k.

[SiliconWizard]

While it's not the prettiest approach, for such "low" frequencies (1 MHz), just using (even relatively large) series resistors for inputs is likely to be enough, rather than adding level shifters. As for outputs, the logic levels of a 3.3V IO should be alright for 5V TTL inputs. Just my 2 cents.

[james_s]

I've done that before and it worked fine for me, don't think I'd do it in a commercial product but it's probably good enough at least as a test.

[brucehoult]

As long as whatever core is used works with a 1MHz clock and the NMI handling works well, I'll be happy.

I don't think I've seen any FPGA soft cores that won't do at least 20 or 30 MHz in a modernish FPGA, and many will do 100+.

I believe that -- unlike many of those 1970s NMOS microprocessors -- you should also be able to run any FPGA soft core with an arbitrarily slow or stopped clock. There were CMOS versions of z80 and 6502 with that capability, but I don't know about 6800.

[james_s]

What happens if you run the older CPUs with a clock that is too slow or stopped? I've never tried that.

I can confirm that the soft cores (that I've tried) can run at arbitrary speeds from single step all the way up to ludicrous speeds relative to the original CPU. I played with one that ran a Z80 at I think 80 MHz.

[chickenHeadKnob]

What happens if you run the older CPUs with a clock that is too slow or stopped? I've never tried that.

registers are DRAM and their bits bleed away without refresh.

[Kleinstein]

If this about a different pinout for a 6801, than the obvious choice would be an adapter board to use a more normal 6801/6803 than an adater board with level shifters for an FPGA.

[Kleinstein]

What happens if you run the older CPUs with a clock that is too slow or stopped? I've never tried that.

registers are DRAM and their bits bleed away without refresh.

It really depends on the CPU. Some type need a minimum speed - though I somewhat doubt it would be really internal DRAM for the registers. There are logic parts like counters that can be implemented easier with capacitors.

Some or the older 8 bit µCs run OK even at 50000 mHz. 

[chickenHeadKnob]

It really depends on the CPU. Some type need a minimum speed - though I somewhat doubt it would be really internal DRAM for the registers. There are logic parts like counters that can be implemented easier with capacitors.

Some or the older 8 bit µCs run OK even at 50000 mHz. 

Yes the parts that had static implementation - typically CMOS versions like 65c02 could be single stepped. Try that with NMOS 6502 and it looses its marbles. There is an area reduction with DRAM cells for registers.

[brucehoult]

What happens if you run the older CPUs with a clock that is too slow or stopped? I've never tried that.

registers are DRAM and their bits bleed away without refresh.

I believe there could also be so on-chip capacitor-based voltage conversion.

[chickenHeadKnob]

What happens if you run the older CPUs with a clock that is too slow or stopped? I've never tried that.

registers are DRAM and their bits bleed away without refresh.

I believe there could also be so on-chip capacitor-based voltage conversion.

Could be, but I thought all the early chips had linear regulators. These days a company like ST makes a marketing point of mentioning if a cpu has switching buck   conversion for power efficiency and supplying limited current for external parts. Example: most of the STM32H7xx parts have onboard smps  along with the standard LDO except for the STM32H750.

[Kleinstein]

The early chips has not on chip regulator at all. The requires supply is provided externally. With the very old ones this could have been multiply voltages (e.g. -5 V, +5 V and maybe +9 V) .  On chip regulator to run the core at a lower voltage is a relatively new thing, maybe starting with MIPS / ARM µCs.

Some flash based µC chips have internal voltage doublers for a higher write votlage for the flash. Just an CPU with no internal flash memory does not need a higher voltage. Some of the early flash chips also needed an external high voltage. Newer ones often include internal clock.

[chickenHeadKnob]

I have just been doing some historical reading. Turns out both 6502 and 6800 had voltage doublers to get 5V operation, so now I don't know. I always had the idea that the first processors were hand optimized and needed minimum area thus dram cells instead of static flip-flops to get the yields high and costs low.

 Original poster probably irritated with me for derailing this thread.

[james_s]

I remember some of the old stuff used weird voltages, some early DRAM chips required at least two different voltages. By the time I started playing with this stuff it was pretty much all 5V though.