Electronics > FPGA

Request for altera/Quartus VGA example



Well I've hit a wall on making my own LCD controller, that is using SDRAM for the frame buffer. I was hoping to first create a custom Qsys component that acts as a avalon master, to write/read to/from the SDRAM controller, essentially a self contained block that writes a pattern to the SDRAM, then reads it back.  It should have a few configuration registers to set the start address, and number of bytes.  This is to prove I can create a master interface, read the SDRAM, and include a timer there so I can time how long it takes to read the number of bytes set - because I wish to know the read speed of both single transfers, and burst transfers.  I was planning on using the NIOS II, along with the JTAG UART for a generic debug interface - terminal to set start address, length, and then start/stop.

I ended up making a rather large state machine, with no real way to test it... I have used model sim and quartus simulator - and it does indeed appear to generate the correct signals for a master interface, and time the reading back part, setting one of the registers with the timer value.

So, time to strip it back to basics.  I noticed this reference design on Alteras website:

Sounds like an ideal starting place, but alas, there are no files to download.  I have asked on the Altera forum, got no response, so I guess its been depreciated, and no-one has a copy. 
So as a last ditch effort, I'm asking here if someone has a simple, verilog, VGA controller with DMA and an Avalon interface.   There is an Avalon master template which I have but this uses a FIFO and no state machine.  The FIFO, whilst probably needed, makes timing how long it would take to read 'x' number of bytes (the SDRAM I have is 8-bit, but of course reads are all 32-bit) difficult.

Perhaps my googling skills are no up to par but I have been searching for a few weeks now, to no avail.  Sure there are VGA examples, and there's even a pre-built component for VGA, but that isn't what I'm interested in, its mostly the master-interface and DMA that I want to see.  Other suggestions have been to just use the built-in components in Qsys but a) connecting components isnt' a great way to learn verilog... and b) a master, slave, SGDMA, blocks are all rather large, leaving little room on the FPGA for the NIOS II and any custom logic, they appear to be over complicated as to be non-application specific.

Normally I wouldn't ask for examples, but as google came up empty...


It's probably not the exact design you're looking for, but look at the DE2_NIOS_HOST_MOUSE_VGA example in this archive. (You could probably also just buy one of the cheap Chinese Cyclone II board off eBay, they come bundled with CDs of all sorts of crap.)

EDIT: This looks like what you're after, but you need to register to download, and I have no idea if that works.

Ah! yes thats it.  Thankfully one can view the files in browser, but I don't see any available verilog thee - they might have just used the built-in libraries.

That ftp link seems to be down, but I'll try later.   Good find sir!

Edit: Just found this: http://www.alteraforum.com/forum/showthread.php?t=19053

They appear to be completely different from the examples Altera provided, these are state machine driven, and look to be ideal as there's examples for block read, burst etc..  Typical.. always find something I need after I post on a forum out of desperation..

It seems the forum mangles FTP links inside bbcode tags, use ftp://ftp.altera.com/up/pub/DE2_demonstrations.zip .


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