Electronics > FPGA

Reset in Verilog isn't working as planned

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ataradov:

--- Quote from: AidanW on March 19, 2023, 12:17:03 am ---I would instead slow the clock down within the counter module instead of using a different module?

--- End quote ---
No need to slow down anything. Your 1 Hz generator would look something like this:


--- Code: ---wire en_1Hz = (counter == 25_000_000);

always@(posedge clk)
begin
    if (reset == 1'b1)
      counter <= 0;
    else if (en_1Hz)
       counter <= 0;
    else
       counter <= counter + 1;
end

--- End code ---

And then the other part:

--- Code: --- always@(posedge clk)
     begin     
      if (reset == 1) // If the reset is high, set the output to 0
           Q <= 4'b0000;   // Not sure why it isn't setting the value to 0 when timer is high
       else if (en_1Hz)
           Q <= Q + 4'b1;
     end

--- End code ---

en_1Hz woud be asserted for one cycle of "clk". And the whole design runs on one clock - "clk".

This way you don't need to think about resets as something special, they are just like any other synchronous signal. And running the design on one (or as few as possible) clocks is always a good idea.

Note that you technically need to compare with 25M-1. Does not matter for indication and general timeouts, but would matter for timekeeping.

BrianHG:

--- Quote from: ataradov on March 19, 2023, 12:22:24 am ---

--- Code: ---wire en_1Hz = (counter == 25_000_000);

always@(posedge clk)
begin
    if (reset == 1'b1)
      counter <= 0;
    else if (en_1Hz)
       counter <= 0;
    else
       counter <= counter + 1;
end

--- End code ---

And then the other part:

--- Code: --- always@(posedge clk)
     begin     
      if (reset == 1) // If the reset is high, set the output to 0
           Q <= 4'b0000;   // Not sure why it isn't setting the value to 0 when timer is high
       else if (en_1Hz)
           Q <= Q + 4'b1;
     end

--- End code ---

en_1Hz woud be asserted for one cycle of "clk". And the whole design runs on one clock - "clk".

This way you don't need to think about resets as something special, they are just like any other synchronous signal. And running the design on one (or as few as possible) clocks is always a good idea.

Note that you technically need to compare with 25M-1. Does not matter for indication and general timeouts, but would matter for timekeeping.

--- End quote ---

Ok, maybe something more like this:


--- Code: ---wire en_1Hz = (counter == 25_000_000);

always@(posedge clk)
begin
    if (reset == 1'b1) begin
        counter <= 1 ; // assuming a 25MHz clock, counting from 0 to 25000000, then back to 0 is a count of 25000001...  I'm also assuming you want a 1 second clock.
        Q       <= 4'b0000 ;   // Not sure why it isn't setting the value to 0 when timer is high
    end else if (en_1Hz) begin
        counter <= 1 ; // assuming a 25MHz clock, counting from 0 to 25000000, then back to 0 is a count of 25000001...
        Q       <= Q + 4'b1 ;
    end else counter <= counter + 1;
end

--- End code ---

ataradov:
It is a matter of preference and overall design. I would not separate very simple things into separate modules, but I also would not combine things this way. It is fine to have two separate always blocks here. It clearly shows the separation of logic and avoids annoying begin/end pairs.

AidanW:
Ahh okay that makes sense. I'm trying to learn better / alternate ways of designing modules so thank you so much for the input! Using separate modules is helpful for me to keep things separate in my head, but it is good to learn the simpler ways to do it.

Thank you!

tchiwam:
https://www.eevblog.com/forum/fpga/and-the-warning-is-gone-simple-divclk-by-n/

I got this to "work", even If I am suspicious of the last clk edge (might generate a glitch IMO)

So I use a register and 2 always@

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