Electronics > FPGA
Reset in Verilog isn't working as planned
AidanW:
Hello all!
So I just started learning Verilog this semester, and I have coded a 4 bit counter to run on LEDs. The counter works great. The only problem is that the reset button does not work as anticipated. When I flip the reset switch, the counter simply stops on whichever number it is currently on. It is meant to set the count to 0 and reset the timer.
Does anyone know what I did wrong? Thank you!
Code below:
# This is my slow clock module. Not rly sure why I need the reset in here, but I am just following examples that I found online.
`timescale 1ns / 1ps
module slowClock(clk, reset, clk_1Hz);
input clk, reset;
output clk_1Hz;
reg clk_1Hz = 1'b0;
reg [27:0] counter;
always@(posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
clk_1Hz <= 0;
counter <= 0;
end
else
begin
counter <= counter + 1;
if ( counter == 25_000_000)
begin
counter <= 0;
clk_1Hz <= ~clk_1Hz;
end
end
end
endmodule
# This is my counter module
`timescale 1ns / 1ps
module fourbitcounter(Q, clk, reset);
input clk, reset; // Declare the inputs as the clock and reset
output [3:0] Q; // Declare the outputs as 4 bit Q
reg [3:0] Q; // Declare Q as a variable
wire clk_1Hz; // Declare the slow clock as a wire
slowClock clock_generator(clk, reset, clk_1Hz); //Instatiate the slow clock
always@(posedge clk_1Hz) // Check for the rising edge of the slow clock
begin
if (reset == 1) // If the reset is high, set the output to 0
Q <= 4'b0000; // Not sure why it isn't setting the value to 0 when timer is high
else // Otherwise, increment the 4 bit Q by 1
Q <= Q + 4'b1;
end
endmodule
ataradov:
Your first part of the code is stopped by the reset, and it generates 1 Hz clock. The second part only has 1 Hz in the sensitivity list, so it would not see the reset until 1 Hz clock is back on (first posedge).
For learning it does not matter that much, but for a real project you would typically have a common always running high speed clock going to all the blocks and blocks would generate one clock cycle long enable signals to perform slower actions.
AK6DN:
Your slow clock module has an asynchronous reset, while your counter module has a synchronous reset.
When you assert reset, your slow clock module sets the clock low and holds it low.
Since your counter module has a synchronous reset, it needs to see a clock edge AND reset asserted to reset.
Your slow clock module is not providing a clock edge.
So change your counter module to use an async reset scheme. Or change your slow clock to be a sync reset scheme.
AidanW:
--- Quote from: AK6DN on March 18, 2023, 11:54:37 pm ---Your slow clock module has an asynchronous reset, while your counter module has a synchronous reset.
When you assert reset, your slow clock module sets the clock low and holds it low.
Since your counter module has a synchronous reset, it needs to see a clock edge AND reset asserted to reset.
Your slow clock module is not providing a clock edge.
So change your counter module to use an async reset scheme. Or change your slow clock to be a sync reset scheme.
--- End quote ---
I changed my counter to look for 1Hz or reset, which fixed it.
Thank you so much! That was really helpful.
AidanW:
--- Quote from: ataradov on March 18, 2023, 10:26:58 pm ---Your first part of the code is stopped by the reset, and it generates 1 Hz clock. The second part only has 1 Hz in the sensitivity list, so it would not see the reset until 1 Hz clock is back on (first posedge).
For learning it does not matter that much, but for a real project you would typically have a common always running high speed clock going to all the blocks and blocks would generate one clock cycle long enable signals to perform slower actions.
--- End quote ---
So for a real project (which I am planning to start soon), I would instead slow the clock down within the counter module instead of using a different module? What does a one clock cycle long enable signal mean?
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