Author Topic: Reverse engineering Anlogic AL3_10 FPGA  (Read 18497 times)

0 Members and 3 Guests are viewing this topic.

Offline Atlan

  • Frequent Contributor
  • **
  • Posts: 531
  • Country: sk
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #100 on: January 24, 2025, 10:01:52 am »
So I did it, turned on the oscilloscope, it went into FEL mode, and then it started programming the flash. But I guess something was compiled incorrectly. It's working now.

Will the bluepill programmer work under WINdows?

Isn't this a problem?
TMR-5009 WARNING: No clock constraint on 4 clock net(s):
   clk_50MHz
   i_mcu_clk_pad
   o_adc1_encB_pad
   sample_read_clock
FNIRSI 1013D Always provide a picture or video with the problem where the parameters of the oscilloscope are visible, and a picture of the diagnostic screen with the values.
Firmware is here (or not) https://github.com/Atlan4/Fnirsi1013D/tree/main/latest%20firmware%20version
 

Offline pcprogrammerTopic starter

  • Super Contributor
  • ***
  • Posts: 4730
  • Country: nl
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #101 on: January 24, 2025, 10:29:49 am »
Will the bluepill programmer work under WINdows?

I don't see a reason why it would not work, but I only do this kind of stuff on Linux. If the TD IDE works under Windows, I assume they provide for the programmer to work under Windows too.

Unfortunately the source code for the programmer is no longer available, at least I could not find it. Just the binary to load into the STM32F103.

Isn't this a problem?
TMR-5009 WARNING: No clock constraint on 4 clock net(s):
   clk_50MHz
   i_mcu_clk_pad
   o_adc1_encB_pad
   sample_read_clock

Not necessarily. Without a clock constraint on it the routing can add delays that may cause it to not work, but my knowledge of setting these constraints fell short. If I remember correctly I tried all kinds of constraint settings on these signals and have it fail with errors.

For me it is also a learning experience, to do these kind of projects.

Offline Atlan

  • Frequent Contributor
  • **
  • Posts: 531
  • Country: sk
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #102 on: January 24, 2025, 12:01:59 pm »
I downloaded the flash content on my oscilloscope: it's the same as yours.
I made a code correction, for AD converter timing.
I've only read 3 scripts from college so far, so I don't have the knowledge yet. I'm attaching a BIN that can be loaded into SPI flash for FPGA, of course the part for I2C is missing so it only works with PECO firmware.
The waveform looks good (at least for channel 1)
What doesn't work is the trigger for rising or falling edge or the trigger level is wrong. To be precise, the trigger for falling edge doesn't work for rising edge and it's even swapped between them.

You please could try it on your oscilloscope, fnirsi_1013d.bin v0.026b thank you

adc1 means converter for channel 1 yellow, and the given converter has 2 parts encA and encB?
         
« Last Edit: January 24, 2025, 12:42:12 pm by Atlan »
FNIRSI 1013D Always provide a picture or video with the problem where the parameters of the oscilloscope are visible, and a picture of the diagnostic screen with the values.
Firmware is here (or not) https://github.com/Atlan4/Fnirsi1013D/tree/main/latest%20firmware%20version
 

Offline pcprogrammerTopic starter

  • Super Contributor
  • ***
  • Posts: 4730
  • Country: nl
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #103 on: January 24, 2025, 01:19:17 pm »
You please could try it on your oscilloscope, fnirsi_1013d.bin v0.026b thank you

If you want me to take a look at it please provide me with the verilog files so I can synthesize things myself and load them directly in via JTAG. Is easier for me.

adc1 means converter for channel 1 yellow, and the given converter has 2 parts encA and encB?

Yes adc1 is for channel 1 and it uses two actual converters that are clocked with encA and encB. These clocks have a 180 degree phase shift between them.

Offline Atlan

  • Frequent Contributor
  • **
  • Posts: 531
  • Country: sk
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #104 on: January 24, 2025, 01:23:24 pm »
ok, sending ALL
« Last Edit: January 24, 2025, 04:14:21 pm by Atlan »
FNIRSI 1013D Always provide a picture or video with the problem where the parameters of the oscilloscope are visible, and a picture of the diagnostic screen with the values.
Firmware is here (or not) https://github.com/Atlan4/Fnirsi1013D/tree/main/latest%20firmware%20version
 
The following users thanked this post: pcprogrammer

Offline pcprogrammerTopic starter

  • Super Contributor
  • ***
  • Posts: 4730
  • Country: nl
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #105 on: January 24, 2025, 05:33:37 pm »
Hi Atlan,

I looked at what you changed and the reduction of the clock divider widths should not make a difference in the working and only reduce the number of logic cells used.

The other change, where you invert the adc1_encA and adc2_encA signals should also not make a difference to what the original code did.

Keep in mind that in HDL actions are taken in parallel in this case. So with the code as it was the two encA registers are set to what the encB registers were before the clock pulse and the encB registers are inverted on the clock pulse. In simulation it works as intended.

With your setup it inverts all four of the signals instead of copying. Internally it most likely is just a difference in the routing.

I have not tested it on the scope as it will do just the same as what I tested 2 years ago.

Also be aware that the original design is as crap as can be. There can be clock domain crossing and meta stability issues with it. If your intent is to improve things, my advice is to start over and make your own design.

Some useful threads might be:
https://www.eevblog.com/forum/fpga/beginner-questions/msg4646935/#msg4646935
https://www.eevblog.com/forum/fpga/what-is-a-beter-write-enable/msg4074163/#msg4074163
https://www.eevblog.com/forum/fpga/why-does-this-dds-code-fail/msg4066636/#msg4066636

BrianHG is very good and helped me quite a bit.

Or take a look at the projects on fpga4fun:
https://www.fpga4fun.com/digitalscope.html

Offline Atlan

  • Frequent Contributor
  • **
  • Posts: 531
  • Country: sk
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #106 on: January 26, 2025, 05:30:44 pm »
any reason why this doesn't work with FIFORAM

Code: [Select]
  sample_memory samples
  (
     .di   ({ i_adc2B_d, i_adc2A_d, i_adc1B_d, i_adc1A_d }),
     //.wrusedw (actual_write_address),
    .clkw  (sample_write_clock),
    .we   (sample_write_enable),
    .rst   (sample_system_reset),

    .do   ({ o_adc2B_d, o_adc2A_d, o_adc1B_d, o_adc1A_d }),
    //.addrb (sample_read_address),
    .clkr  (sample_read_clock),
    .re   (sample_read_enable)
    //.ceb   (1'b1)
  );
FNIRSI 1013D Always provide a picture or video with the problem where the parameters of the oscilloscope are visible, and a picture of the diagnostic screen with the values.
Firmware is here (or not) https://github.com/Atlan4/Fnirsi1013D/tree/main/latest%20firmware%20version
 

Offline pcprogrammerTopic starter

  • Super Contributor
  • ***
  • Posts: 4730
  • Country: nl
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #107 on: January 26, 2025, 07:41:52 pm »
any reason why this doesn't work with FIFORAM

I have no idea. But a FIFO is not what you would need to make it work. A circular buffer is what is a far better approach, were the samples are continuously stored and when the trigger is seen, a count down starts to limit the number of samples after the trigger. Record the trigger point for read back by the MCU.

The trigger part should always run at the maximum sample rate. For the writing in the circular buffer the sampling clock is lowered. This means you throw away a lot of samples, but the trigger is much more accurate.

To get a better help on FPGA matters you best start a new thread with the specific questions about your problems with the design. There are others on the forum with much more knowledge on FPGA than I have.

Offline Atlan

  • Frequent Contributor
  • **
  • Posts: 531
  • Country: sk
Re: Reverse engineering Anlogic AL3_10 FPGA
« Reply #108 on: January 26, 2025, 11:03:41 pm »
I would use FIFoRAM to get a lot of sample memory. For periodic signals it doesn't matter, just take 800 samples and activate the trigger search. If found, the value at which the FIFO is located is written as the trigger address. The chance that the trigger will be found within 100 samples is very high. With the possibility of 32000 samples. The question is the duration of loading 32000 samples into the uP. But that could also be handled in the FPGA, since we know the trigger address.
FNIRSI 1013D Always provide a picture or video with the problem where the parameters of the oscilloscope are visible, and a picture of the diagnostic screen with the values.
Firmware is here (or not) https://github.com/Atlan4/Fnirsi1013D/tree/main/latest%20firmware%20version
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf