Ring Oscillator to determine delay

[steamedhams]

G'day folks.

I have implemented a Ring Oscillator and then I've included an extra 2 inverters located in another tile a few positions away from the Ring Oscillator.

I've done this because I want to determine the delay caused by the routing.

The ring oscillator should allow me to approximately calculate the delay of one inverter which I can than subtract from the overall delay, giving me the delay of the route.

Unfortunately, the frequency of the oscillator is jumping around a little and isn't very different from that of the oscillator...

Is there better way to measure the delay introduced by the routes???
 
i am going to try and increase the number of inverters to see if I can slow things down... But I am not so confident with that approach. Also, increasing the number of inverters increases the error in my approximation.

[Bassman59]

Remember that routing delay varies with temperature and voltage ...

[nvmR]

Interesting problem op.
If I understand correctly, you are outputing both options to pins. Consider the fact that there are different "pin delays" between each output on the silicon die and the corresponding ball/pin.
I assume you are using some sort of constraints to make sure the placement is in the location of your choice?

My approach would be somewhere in the ballpark of implementing two counters, and use them to output a digital reading which would correspond to the delay, by counting a certain number of clock cycles of a inverter with a delay and without a delay. This removes the jitter of the ring oscillators from the picture - because it is averaged over time.
This however adds other problems - as adding delay changes the behavior of the ring oscillator, so another approach is to XOR the delayed oscillator with an non-delayed oscillator, and count a reference clock.
Again though, these approaches give you the affect of routing along with capacitance which changes the oscillator frequency.

All this being said, a ring oscillator may not be the best of choices for this, as it is very sensitive to additional capacitance, and to process and voltage.

[NorthGuy]

Is there better way to measure the delay introduced by the routes???

Sure. Add 1000 LUTs in series. Make them part of  the oscillator loop and observe the change in frequency.

Or, you can do manual routing without even using extra LUTs. That's what manufacturers do to characterize routing delays. It's all known and used to run STA. Why do you want to measure routing delays on your own?

There's about 3x variation in delay depending on process, temperature, voltage, and aging. You can use them in forensic work. People use delays to identify the specific FPGA chip, detect if the chip was used before, etc.