S_AXI_AWREADY always red X in Vivado simulator

[JohnnyMalaria]

I'm trying to write data to a Xilinx Block Memory Generator 8.4 configured with AXI4-Lite interfaces.

The attached screenshot of the BMG instance in my test bench shows my problem - S_AXI_AWREADY signal from the BMG never asserts. Instead, it remains red X and so my write stalls.

This is a snippet from my FSM:

Code: [Select]

                when WRITE_AWADDR =>
                    m_axi_wdata <= s_data;
                    m_axi_awvalid <= '1';               
                    m_axi_wvalid <= '1';
                    if m_axi_awready = '1' then -- slave ready to receive write address and control
                        state <= WRITE_WDATA;
                    end if;
                                       
                when WRITE_WDATA =>
                    if m_axi_wready = '1' then -- slave ready to receive write data
                        state <= SEND_READY;
                        if s_last = '1' then
                            state <= PROCESS_LAST;
                        end if;
                        s_total_written <= s_total_written + 1;
                    end if;

[asmi]

I *highly* recommend using free AXI Verification IP for anything AXI to verify that your bus transfers are compliant with the spec. I use it all the time when designing anything AXI before I ever connect my module to real AXI bus. It can be configured to simulate master, slave or just a passthrough, the latter mode is for verification, but I typically use it as either master or slave depending of whether the module I'm working on is a slave or master.

There is one caveat - AXI VIP is written in 100% SystemVerilog, and you will need to use that language for the testbench code because VDHL and Verilog do not support some of the advanced SV features which
 are used for that IP. You DUT can be designed using any HDL, the SV requirement is only for the testbench code.

In your case I noticed that you don't assert bready and arvalid to valid values (high or low), who knows maybe that screws something up. And - just in case - check the connectivity, AXI has got quite a bit of signals, so it's easy to miss one or connect it to something else by accident. If all of that checks out, please post the full source code of the module with a problem, so that we can actually simulate it to find an issue.

[xlnx]

There is one caveat - AXI VIP is written in 100% SystemVerilog, and you will need to use that language for the testbench code because VDHL and Verilog do not support some of the advanced SV features which
 are used for that IP. You DUT can be designed using any HDL, the SV requirement is only for the testbench code.

Not entirely true - there is UVVM which uses VHDL and is completely free: https://bitvis.no/dev-tools/uvvm/

I've been using UVVM extensively and I highly recommended it - even works great with the free Intel version of ModelSim (also when your target is Xilinx).

[asmi]

Not entirely true - there is UVVM which uses VHDL and is completely free: https://bitvis.no/dev-tools/uvvm/

What is not entirely true? That AXI VIP is not written in 100% SystemVerilog? Of course that is entirely true. And it's a great tool that I use all the time.

[xlnx]

Not entirely true - there is UVVM which uses VHDL and is completely free: https://bitvis.no/dev-tools/uvvm/

What is not entirely true? That AXI VIP is not written in 100% SystemVerilog? Of course that is entirely true. And it's a great tool that I use all the time.

UVVM is written entirely in VHDL, and includes verification IP for all flavors of AXI. SystemVerilog is not the only solution for verification, as I interpreted your statement.

[asmi]

UVVM is written entirely in VHDL, and includes verification IP for all flavors of AXI. SystemVerilog is not the only solution for verification, as I interpreted your statement.

Well you should read what I actually said, as opposed to what you think I have said.
Even though my opinion of VHDL is well known to frequents here, it is beside the point.

[JohnnyMalaria]

Just to note that I ended up using a different approach as shown below which works correctly when implemented on my Zynq board. i.e., I generated native BRAM signals in my module and use the Xilinx IP to do the AXI stuff.

[xlnx]

UVVM is written entirely in VHDL, and includes verification IP for all flavors of AXI. SystemVerilog is not the only solution for verification, as I interpreted your statement.

Well you should read what I actually said, as opposed to what you think I have said.
Even though my opinion of VHDL is well known to frequents here, it is beside the point.

This is what you actually wrote:

There is one caveat - AXI VIP is written in 100% SystemVerilog, and you will need to use that language for the testbench code because VDHL and Verilog do not support some of the advanced SV features which
 are used for that IP. You DUT can be designed using any HDL, the SV requirement is only for the testbench code.

Anyone who reads your statement may come to believe that the only way to use an AXI verification IP is by having access to a SystemVerilog simulator, which is simply not true. I was just pointing out that it can also be done with VHDL and UVVM - for free! Do you not believe this is useful information? A SystemVerilog simulator is extremely expensive and out of reach for most people. No need for getting defensive. I'm not trying to start a war.

[asmi]

Anyone who reads your statement may come to believe that the only way to use an AXI verification IP is by having access to a SystemVerilog simulator, which is simply not true.

Yes it is true. AXI VIP is written using SV, and it uses some SV features like virtual interfaces, so you will need a SV testbench to use it to the full extent.

I was just pointing out that it can also be done with VHDL and UVVM - for free! Do you not believe this is useful information?

No I do not believe that is useful, at least for me.

A SystemVerilog simulator is extremely expensive and out of reach for most people.

And that is absolutely NOT true. Vivado/Vitis includes a fully featured mixed-language simulator which supports SV, and it's absolutely free!

[xlnx]

Anyone who reads your statement may come to believe that the only way to use an AXI verification IP is by having access to a SystemVerilog simulator, which is simply not true.

Yes it is true. AXI VIP is written using SV, and it uses some SV features like virtual interfaces, so you will need a SV testbench to use it to the full extent.

Now I understand why you don't get it. You talk about AXI VIP, as if there is only one VIP in existence that support AXI. I just told you there exists VHDL based AXI VIP within UVVM, which you just keep denying. For those of us that use VHDL, that is an absolutely fantastic tool.

I was just pointing out that it can also be done with VHDL and UVVM - for free! Do you not believe this is useful information?

No I do not believe that is useful, at least for me.

Not useful to you doesn't mean it's not useful to everyone else.

A SystemVerilog simulator is extremely expensive and out of reach for most people.

And that is absolutely NOT true. Vivado/Vitis includes a fully featured mixed-language simulator which supports SV, and it's absolutely free!

Thanks for letting me know - that was certainly not the case just a few years ago, when only a small subset of SV was supported. I see that UVM is now supported, which is great.

[asmi]

Now I understand why you don't get it. You talk about AXI VIP, as if there is only one VIP in existence that support AXI. I just told you there exists VHDL based AXI VIP within UVVM, which you just keep denying. For those of us that use VHDL, that is an absolutely fantastic tool.

I never said that it's the only one in existence. I merely recommended the tool I use myself. So again - try reading what I actually said, as opposed to arguing with what you think I have said.