SD card/SDIO 3.0 level translation solution

[asmi]

I'm working on adding SD/SDIO card slot to my FPGA board, but there is a problem - UHS-I cards require switching from 3.3V to 1.8 V logic level during the course of work in order to get maximum performance out of cards. As changing IO standard on a fly is not possible, the only solution is some sort of level translator. Unfortunately the only solution I've found in stock (IP4856CX25) is 0.4 mm pitch BGA which require microvias and raises the price of a board to a stratosphere. So I wonder if anybody over here has any solution for this problem.

[sd]

http://www.ti.com/lit/ds/symlink/txs02612.pdf

[asmi]

http://www.ti.com/lit/ds/symlink/txs02612.pdf

This one is only rated to 60 MHz, while SDR104 requires 208 MHz clock, so it's not SD3.0 compliant and can't get full UHS-I throughput. Some other TI parts like SN74AVCA406 are also no good as they are rated up to 95 MHz.
The only solution I can think of right now would be to use 1.8V logic standard on FPGA, but then use hi-bandwidth analog switch (like TS3A27518) to switch in 1.8->3.3 V voltage translator during boot-up when 3.3V signalling is required, but switch it off to straight-through connection to FPGA once the bus is switched to 1.8 V. Since SD boot sequence until bus voltage switch is short and no high frequency is required, I can get away with pretty much any translator as long as channel-to-channel skew won't be too large,

[mark03]

As I hope to design an I.MX RT10xx board in the near future, and these MCUs claim to support UHS-I, I was curious how NXP handled this on their eval board.  Turns out they have a separate VCC for the IO bank containing the SD signals, and this rail comes from an adjustable regulator which they switch between 1.8 and 3.3 volts on the fly.

I am a rank beginner with FPGAs.  What happens if you define the IO standard as LVCMOS 3.3 and then step VCCO for that IO bank down to 1.8V?  What does switching the IO standard between LVCMOS 1.8/2.5/3.3 actually *do*, physically?

[Marco]

I have no idea how to do it smart ... but I have an idea how to do it expensively.

Connect the SD-connector to something like a MAX4996 and then to slow level converter to do communication at HS, then when it switches SDR104 switch to a separate set of pins on your FPGA with the MAX4996. Needs extra pins on the FPGA, but only one IO voltage.

[asmi]

I am a rank beginner with FPGAs.  What happens if you define the IO standard as LVCMOS 3.3 and then step VCCO for that IO bank down to 1.8V?  What does switching the IO standard between LVCMOS 1.8/2.5/3.3 actually *do*, physically?

FPGA I/O blocks have different drivers for different standards. Besides since the bank has 50 I/O pins and SD interface only uses 6, I will have to solve reverse problem for other 44 pins, which don't need such voltage shenanigans

[asmi]

I have no idea how to do it smart ... but I have an idea how to do it expensively.

Connect the SD-connector to something like a MAX4996 and then to slow level converter to do communication at HS, then when it switches SDR104 switch to a separate set of pins on your FPGA with the MAX4996. Needs extra pins on the FPGA, but only one IO voltage.

That's essentially what I've proposed in my first reply, except since there is already voltage converter, you might as well reuse same pins as you will never have to use them both at the same time. The good thing about TS3A27518 switch is that it's got 6 SPDT switches which is exactly how much I need.

[Marco]

Oh, didn't see that. Capacitive load of the TS3A27518 is high though ... it pushes you past the recommendations of parasitic capacitance all on it's own. With wide traces (ie. lower impedance) and a smaller series resistance than normal you might be able to get away with it, but with MAX4996 you wouldn't have to go that far (6 pF).

[asmi]

Oh, didn't see that. Capacitive load of the TS3A27518 is high though ... it pushes you past the recommendations of parasitic capacitance all on it's own. With wide traces (ie. lower impedance) and a smaller series resistance than normal you might be able to get away with it, but with MAX4996 you wouldn't have to go that far (6 pF).

I don't like that I will need two MAX4996 ICs, which can introduce bus skew, also they are quite expensive Will see if I will be able to find any other switch with low enough bus loading.

[asmi]

Looks like I've found the right switch! It's TS3DDR4000. I bit of an overkill as I only need 6 lines, and the specs are way above and beyond, but - hey - it's still cheaper than MAX4996!

[Marco]

Nice find, not something I would have thought to look at.

[asmi]

Another thing I realized after reading SD spec is that I can get away with only single bit bidirectional voltage translator + one unidirectional one (for clock) as all commands required to switch to 1.8V don't require any data transfers over DAT lines.

[thobie]

Yeah, struggling with the same idiotic implementation problem with microsd card interface - and the LVS ”low voltage signaling” cards are not yet here unfortunately. Anyone tried how the modern UHS-I cards behave supplied with just between 1.8V and 2.7V?

Even Xilinx is using in their development boards some silly 60USD adapter spcaer PCB to get the 0.4mm BGA to work.  What FPGA are you using? Planned to do this for Xilinx Zynq Ultrascale+.

I was already going to use discrete >200MHz level translators from TI, good to know that if initialization/level change to 1.8v is done in SPI mode, not all lines are used. But why only two level translators - or one of those bi-directional not uni? Controller to card data input level 1.8V could be in the range of ”high” signal if card supplied with 2.7V, so could get without level translation. Data from card to controller with unidirectional translator? Clock could survive without translation when AC coupled, haven’t done the math is it so also in practice.

[asmi]

Yeah, struggling with the same idiotic implementation problem with microsd card interface - and the LVS ”low voltage signaling” cards are not yet here unfortunately. Anyone tried how the modern UHS-I cards behave supplied with just between 1.8V and 2.7V?

Yea I've never seen any LV cards "in the wild", which would actually be good enough for my needs.

Even Xilinx is using in their development boards some silly 60USD adapter spcaer PCB to get the 0.4mm BGA to work.  What FPGA are you using? Planned to do this for Xilinx Zynq Ultrascale+.

I plan to use it with 7 series FPGAs. There are several projects where I need this in both microSD and full-size SDIO format. I'm currently investigating how much would it cost for me to make such module, and I will also need to figure out how to get good enough SI as 208 MHz is a no joke. If the price will be good, maybe I will put up a Kickstarter campaign or something to get it out in the wild, as larger batch will means lower per-unit price.

I was already going to use discrete >200MHz level translators from TI, good to know that if initialization/level change to 1.8v is done in SPI mode, not all lines are used. But why only two level translators - or one of those bi-directional not uni? Controller to card data input level 1.8V could be in the range of ”high” signal if card supplied with 2.7V, so could get without level translation. Data from card to controller with unidirectional translator? Clock could survive without translation when AC coupled, haven’t done the math is it so also in practice.

SD spec says startup clock can be as low as 400 kHz, so AC-coupling is not going to work.
As for the shortest path to 1.8V - all data exchange is done over CMD line - so bidirectional translator is needed here, and another unidirectional one is for clock. There is a nice command sequence diagram in the spec to get into 1.8V, and none of commands mentioned there do any data exchange over data lines. Finally, 1.8V mode only works in 4-bit mode (over all data lines).
Also SPI is not available in 1.8V mode and once 1.8V is turned on, the only way to turn it off (so that SPI could be re-enabled) is to power-cycle the card.

[mark03]

I had occasion to come back to this question today, and had a wild (and potentially stupid) idea:

The STM32H7 I am looking at does not have > 1 independent IO bank, however the IO rail is separate from the core, DCDC input, etc.  You can probably see where this is going...

If
(1) sleep current on the SD card is acceptable (usually less than 500 uA from what I understand),
(2) the application can require the SD card to be present at power up, and
(3) 1.8V is a satisfactory IO standard for everything else connected to the MCU,
then in principle you can design a switchable 3.3/1.8 VDD and supply it to both the card and the MCU.  Immediately after MCU reset, VDD=3.3V.  Perform the card initialization and voltage change while all of the other IOs are still tri-stated.  Then, switch the VDD rail to 1.8V and proceed to configure other GPIOs/peripherals, everyone operating harmoniously at 1.8V.

Alternatively, does anyone have an up-to-date recipe for doing the proper level translation without relying on chip-scale BGAs with 0.4mm pitch?

[bugnate]

Yea I've never seen any LV cards "in the wild", which would actually be good enough for my needs.

I had thought that LVS support was implied with A2 standard, which is more or less available, no?
EDIT: Just looked at the timestamps. D'oh.

[mark03]

EDIT: Just looked at the timestamps. D'oh.

Yeah, sorry if that caught someone off guard.  OTOH, the question posed by the thread is still very much current and open, so...

If a nontrivial fraction of new SD cards actually don't need the voltage switching dance, that would be news to me.  Very welcome news.

[mark03]

I did some more digging, and found that yes, indeed "A2" implies "LVS".  A2 cards are still not very common, but they are starting to appear.  Unfortunately, this has only led to more questions:

The SD spec does not discuss LVS directly; instead it refers to a "Low Voltage Interface Addendum" which has not leaked out online.  If you google it you will find some conversations by Linux kernel developers attempting to figure out why A2 cards are breaking certain hardware, and that's about it.  Anyway, if the writing style of that addendum is anything like that of the main SD spec, reading it may not help much

On the kernel mailing list they concluded that LVS only lets you start *communication* at 1.8V; according to this view, the card must still be supplied with 3.3V power until it is negotiated to 1.8V.  That seems odd, but it's the only interpretation I've been able to find by someone who actually read the spec.  At least it would solve the bus voltage translation issue.

Then there is this from the SD Association marketeers:

LVS cards are designed to start command/response communication either with 3.3V signaling modes or 1.8V signaling modes. An identification sequence after power up, called LVS Identification, is used to select either signaling mode. LVS cards can identify LVS hosts via the LVS Identification by checking the specified clock period on SDCLK pin and signal lines level at clock edge. If an LVS host is identified, the LVS card selects 1.8V signaling; otherwise, it selects 3.3V signaling.

I have no idea what this means, but it does not give me confidence that legacy UHS-I capable microcontrollers can use the LVS feature.  It makes it sound like there is some new wrinkle in the initialization process. 

[Rasz]

I have no idea what this means, but it does not give me confidence that legacy UHS-I capable microcontrollers can use the LVS feature.  It makes it sound like there is some new wrinkle in the initialization process. 

sounds like autodetect to me

[EEEnthusiast]

If you could do a small board with the IP4856CX25, the SD card connector and another high speed connector to the FPGA board, your problem could be solved. The small board wont cost much even with the microvias. You could use fine pitch board to board connectors and add extra mechanical strength using nuts, bolts and spacers.

[asmi]

If you could do a small board with the IP4856CX25, the SD card connector and another high speed connector to the FPGA board, your problem could be solved. The small board wont cost much even with the microvias. You could use fine pitch board to board connectors and add extra mechanical strength using nuts, bolts and spacers.

I did investigate this solution, and it turned out very expensive unless I invest a ton of money and make a very large run. But more broadly speaking, this whole thing sounds like a solution to a problem that shouldn't exist in the first place. I left this project alone for now, but I would skill very much like to know if any sane solution exists.

[mark03]

But more broadly speaking, this whole thing sounds like a solution to a problem that shouldn't exist in the first place. I left this project alone for now, but I would skill very much like to know if any sane solution exists.

So would I!  Very curious to hear if someone has tried the A2 cards in a 1.8V-only system.  Agree that the whole situation is sort of ridiculous.  It would make a good case study in the perils of backwards compatibility.

[asmi]

This is an old topic, but now we finally have a proper solution: https://www.nxp.com/part/NVT4858HK#/ This part is available in QFN-like package.

[mark03]

Thanks for sharing this!

I am still wondering though, Do we know if level translation is actually required in a 1.8V system, where you have the option of choosing the SD card yourself?  Interested in both "official" and "unofficial" answers.

[mroberto]

From the datasheet:

...
- Support SD/SIM card supply voltages with range of 1.65 V to 3.6 V
- Host microcontroller operating voltage range: 1.08 V to 1.95 V
...

Isn't 1.95 V a little bit too low on the microcontroller side?