Should I use one big always block or several smaller ones?

[parkerlewis404]

I have very little hdl experience, so wondering if anyone has any thoughts on how something like this is usually structured..

I want to serially transmit a byte to an external device .  The serial clock comes from that device and expects my data to change on the falling edge.   
Once all the bits have been shifted out, the device will shift out its data after 10-100usec..  and my fpga should latched each bit on the rising edge.  Again, the device outputs the serial clock.

I'm wondering if it's best to make one giant always block, that runs on an internal fast clock to keep track when to send the request, as well monitoring the clock level in order to transmits/receives the data at the right time.  The slower serial clock would not be part of the sensitivity list and would just be sampled.     Or should I separate the data-request time-keeping from the tx and rx process.

Code: [Select]

always @(negedge SCLK )
begin
        // other always block will set register flag when time to shift out data
if ( dataOutputTime == 1'b1 )
// state-mach to output data bit-by-bit
end
always @(posedge SCLK )
begin
        // other always block will set register flag when time to shift in data
if ( dataInputTime == 1'b1 )
// state-mach to latch incoming data bit-by-bit
end

always@(negedge PCLK or negedge PRESETN)
    // Check counter and if time to send , dataOutputTime <= 1
    // If data has been transmitted, then receive data dataInputTime <= 1


VERSUS..

// PCLK >> SCLK
always@(posedge PCLK or negedge PRESETN)
begin
        case (fsm)
3'b000 - 3'b111:
                 // Check if time to send.. if so:
                 // request data by updating output on every falling SCLK (not in sensitivity list)               
3'b100 : // get data 
                     // get input data by looping on every rising edge of SCLK  (not in sensitivity list)       

Would love to hear any thoughts on this.. maybe there's other/better ways to do this.   I've found plenty of syntax documentation, but not much in terms of the thinking that goes behind architecting a solution.
Thanks!

[hamster_nz]

My preference is for every block to be logically complete (I.e. do the whole task). Sometimes a module might include more that one task (so an interface might have a  TX and RX block).

It irks me iwhen you get things that need both asynchronous and clocked logic.

The traditional two process design methodology is a bit like training wheels - great to start with but soon becomes redundant.