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Simulate Xilinx libraries on Vivado

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gauravmp:
Hi,

I'm trying to use the library PLLE2_BASE (a pll) to get a clock. In my test bench, I a generated the system clock which is the input to the FPGA. But, when I see the output of the resulting clock, it is always at 0. So, I'm wondering if this is a thing with libraries that since it uses the hardware of the FPGA, it is incapable of being simulated on the software. Can someone tell me if I'm right or wrong?

Thanks

hamster_nz:
I regularly simulate PLLs without any issue. I suspect a bug in your code or test bench.

If you post your code here I'll have a gander....

gauravmp:
Thanks for the offer. For now, I'm just trying to see how I can use the PLL. Here's my top level module:

module uart(
   clk,
   clk_baud,
   clk_out
);

input clk;
output clk_baud;
output clk_out;


wire clk;
wire clk_baud;
wire clk_out;

assign clk_out = clk;



PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(20), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(20.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(40),
//.CLKOUT1_DIVIDE(1),
//.CLKOUT2_DIVIDE(1),
//.CLKOUT3_DIVIDE(1),
//.CLKOUT4_DIVIDE(1),
//.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
//.CLKOUT1_DUTY_CYCLE(0.5),
//.CLKOUT2_DUTY_CYCLE(0.5),
//.CLKOUT3_DUTY_CYCLE(0.5),
//.CLKOUT4_DUTY_CYCLE(0.5),
//.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
//.CLKOUT1_PHASE(0.0),
//.CLKOUT2_PHASE(0.0),
//.CLKOUT3_PHASE(0.0),
//.CLKOUT4_PHASE(0.0),
//.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(clk_baud),
//.CLKOUT1(CLKOUT1),
//.CLKOUT2(CLKOUT2),
//.CLKOUT3(CLKOUT3),
//.CLKOUT4(CLKOUT4),
//.CLKOUT5(CLKOUT5),
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
// Status Port: 1-bit (each) output: PLL status ports
.LOCKED(LOCKED), // 1-bit output: LOCK
// Clock Input: 1-bit (each) input: Clock input
.CLKIN1(clk), // 1-bit input: Input clock
// Control Ports: 1-bit (each) input: PLL control ports
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
);
// End of PLLE2_BASE_inst instantiation

endmodule



And here's my test bench:

module uart_tb(

    );
reg sys_clk;
wire baud_clk;


uart inst(
    .clk(sys_clk),
    .clk_baud(baud_clk)

    );


initial
begin
    sys_clk <= 1;

end



always #5
sys_clk <= ~sys_clk;



endmodule

No matter how I change the values, I always get the graph I attached.

Will appreciate any help

xygor:
The waveform looks like it might be correct for the code you posted.
Some observations:
CLKFBIN is not connected.
Are there any warning messages from the PLL behavioral model?
Did you wait long enough for the correct output to be produced? (the real PLL does not put out what it is programmed to do until it is locked.)
RST is not connected.  You should reset the PLL at the simulation startup.

xygor:
I forgot one other thing: use the core generator to make what you want, if for nothing else, as an example.  There are a lot of tedious little details to get right.
(sorry to steal hamster_nz's thunder.  hamster_nz gives good advice.)

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