Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx100
Project ID (random number) 61d4773a20c74e50a81b312458875628.BD19ECB4BFF6419EA9562F423FC482C1.1 Target Package: fgg484
Registration ID _ Target Speed: -3
Date Generated 2021-05-31T16:46:59 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz CPU Speed 3492 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz CPU Speed 3492 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 8-bit comparator lessequal=1
Counters=2
  • 32-bit up counter=1
  • 8-bit up counter=1
Registers=1
  • Flip-Flops=1
MiscellaneousStatistics
  • AGG_BONDED_IO=14
  • AGG_IO=14
  • AGG_SLICE=22
  • NUM_BONDED_IOB=14
  • NUM_BSFULL=41
  • NUM_BSLUTONLY=22
  • NUM_BSUSED=63
  • NUM_BUFG=1
  • NUM_BUFIO2=1
  • NUM_LOGIC_O5ANDO6=2
  • NUM_LOGIC_O5ONLY=36
  • NUM_LOGIC_O6ONLY=23
  • NUM_LUT_RT_DRIVES_CARRY4=2
  • NUM_LUT_RT_EXO6=2
  • NUM_LUT_RT_O6=36
  • NUM_PLL_ADV=1
  • NUM_SLICEL=10
  • NUM_SLICEX=12
  • NUM_SLICE_CARRY4=10
  • NUM_SLICE_CONTROLSET=1
  • NUM_SLICE_CYINIT=103
  • NUM_SLICE_FF=41
  • NUM_SLICE_UNUSEDCTRL=11
  • NUM_UNUSABLE_FF_BELS=7
NetStatistics
  • NumNets_Active=90
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=10
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_BUFIOINP=1
  • NumNodesOfType_Active_CLKPIN=13
  • NumNodesOfType_Active_CLKPINFEED=6
  • NumNodesOfType_Active_DOUBLE=33
  • NumNodesOfType_Active_GENERIC=15
  • NumNodesOfType_Active_GLOBAL=16
  • NumNodesOfType_Active_INPUT=9
  • NumNodesOfType_Active_IOBIN2OUT=13
  • NumNodesOfType_Active_IOBOUTPUT=13
  • NumNodesOfType_Active_LUTINPUT=83
  • NumNodesOfType_Active_OUTBOUND=63
  • NumNodesOfType_Active_OUTPUT=77
  • NumNodesOfType_Active_PADINPUT=13
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=24
  • NumNodesOfType_Active_PINFEED=110
  • NumNodesOfType_Active_QUAD=16
  • NumNodesOfType_Active_SINGLE=32
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=7
  • IOB-IOBS=7
  • SLICEL-SLICEM=10
  • SLICEX-SLICEM=1
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • BUFIO2=1
  • BUFIO2_BUFIO2=1
  • CARRY4=10
  • HARD0=2
  • IOB=14
  • IOB_IMUX=1
  • IOB_INBUF=1
  • IOB_OUTBUF=13
  • LUT5=38
  • LUT6=63
  • PAD=14
  • PLL_ADV=1
  • PLL_ADV_PLL_ADV=1
  • REG_SR=41
  • SLICEL=10
  • SLICEX=12
 
Configuration Data
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:13]
  • SLEW=[SLOW:13]
  • SUSPEND=[3STATE:13]
PLL_ADV
  • RST=[RST:1] [RST_INV:0]
PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLK_FEEDBACK=[CLKFBOUT:1]
  • COMPENSATION=[INTERNAL:1]
  • PLL_ADD_LEAKAGE=[2:1]
  • PLL_AVDD_COMP_SET=[2:1]
  • PLL_CLAMP_BYPASS=[FALSE:1]
  • PLL_CLAMP_REF_SEL=[1:1]
  • PLL_CLK0MX=[0:1]
  • PLL_CLK1MX=[0:1]
  • PLL_CLK2MX=[0:1]
  • PLL_CLK3MX=[0:1]
  • PLL_CLK4MX=[0:1]
  • PLL_CLK5MX=[0:1]
  • PLL_CLKBURST_CNT=[0:1]
  • PLL_CLKBURST_ENABLE=[TRUE:1]
  • PLL_CLKCNTRL=[0:1]
  • PLL_CLKFBMX=[0:1]
  • PLL_CLKFBOUT2_EDGE=[TRUE:1]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKFBOUT_EDGE=[TRUE:1]
  • PLL_CLKFBOUT_EN=[FALSE:1]
  • PLL_CLKFBOUT_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT0_EDGE=[TRUE:1]
  • PLL_CLKOUT0_EN=[FALSE:1]
  • PLL_CLKOUT0_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT1_EDGE=[TRUE:1]
  • PLL_CLKOUT1_EN=[FALSE:1]
  • PLL_CLKOUT1_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT2_EDGE=[TRUE:1]
  • PLL_CLKOUT2_EN=[FALSE:1]
  • PLL_CLKOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT3_EDGE=[TRUE:1]
  • PLL_CLKOUT3_EN=[FALSE:1]
  • PLL_CLKOUT3_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT4_EDGE=[TRUE:1]
  • PLL_CLKOUT4_EN=[FALSE:1]
  • PLL_CLKOUT4_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT5_EDGE=[TRUE:1]
  • PLL_CLKOUT5_EN=[FALSE:1]
  • PLL_CLKOUT5_NOCOUNT=[TRUE:1]
  • PLL_CLK_LOST_DETECT=[FALSE:1]
  • PLL_CP=[1:1]
  • PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]
  • PLL_CP_REPL=[1:1]
  • PLL_CP_RES=[0:1]
  • PLL_DIRECT_PATH_CNTRL=[TRUE:1]
  • PLL_DIVCLK_EDGE=[TRUE:1]
  • PLL_DIVCLK_NOCOUNT=[TRUE:1]
  • PLL_DVDD_COMP_SET=[2:1]
  • PLL_EN=[FALSE:1]
  • PLL_EN_DLY=[TRUE:1]
  • PLL_EN_LEAKAGE=[2:1]
  • PLL_EN_TCLK0=[TRUE:1]
  • PLL_EN_TCLK1=[TRUE:1]
  • PLL_EN_TCLK2=[TRUE:1]
  • PLL_EN_TCLK3=[TRUE:1]
  • PLL_EN_VCO0=[FALSE:1]
  • PLL_EN_VCO1=[FALSE:1]
  • PLL_EN_VCO2=[FALSE:1]
  • PLL_EN_VCO3=[FALSE:1]
  • PLL_EN_VCO4=[FALSE:1]
  • PLL_EN_VCO5=[FALSE:1]
  • PLL_EN_VCO6=[FALSE:1]
  • PLL_EN_VCO7=[FALSE:1]
  • PLL_EN_VCO_DIV1=[FALSE:1]
  • PLL_EN_VCO_DIV6=[TRUE:1]
  • PLL_INTFB=[0:1]
  • PLL_IO_CLKSRC=[0:1]
  • PLL_LFHF=[3:1]
  • PLL_LOCK_FB_DLY=[3:1]
  • PLL_LOCK_REF_DLY=[5:1]
  • PLL_MAN_LF_EN=[TRUE:1]
  • PLL_NBTI_EN=[TRUE:1]
  • PLL_PFD_CNTRL=[8:1]
  • PLL_PFD_DLY=[1:1]
  • PLL_PWRD_CFG=[FALSE:1]
  • PLL_REG_INPUT=[TRUE:1]
  • PLL_RES=[1:1]
  • PLL_SEL_SLIPD=[FALSE:1]
  • PLL_SKEW_CNTRL=[0:1]
  • PLL_TEST_IN_WINDOW=[FALSE:1]
  • PLL_VDD_SEL=[0:1]
  • PLL_VLFHIGH_DIS=[TRUE:1]
  • RST=[RST:1] [RST_INV:0]
REG_SR
  • CK=[CK:41] [CK_INV:0]
  • LATCH_OR_FF=[FF:41]
  • SRINIT=[SRINIT0:41]
  • SYNC_ATTR=[ASYNC:41]
SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
SLICEX
  • CLK=[CLK:3] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=8
  • CO3=8
  • CYINIT=2
  • DI0=10
  • DI1=10
  • DI2=10
  • DI3=8
  • O0=10
  • O1=10
  • O2=10
  • O3=10
  • S0=10
  • S1=10
  • S2=10
  • S3=10
HARD0
  • 0=2
IOB
  • I=1
  • O=13
  • PAD=14
IOB_IMUX
  • I=1
  • OUT=1
IOB_INBUF
  • OUT=1
  • PAD=1
IOB_OUTBUF
  • IN=13
  • OUT=13
LUT5
  • O5=38
LUT6
  • A1=2
  • A2=2
  • A3=2
  • A4=35
  • A5=18
  • A6=62
  • O6=63
PAD
  • PAD=14
PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • RST=1
PLL_ADV_PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • RST=1
REG_SR
  • CK=41
  • D=41
  • Q=41
SLICEL
  • A4=8
  • A5=2
  • A6=10
  • AMUX=2
  • AQ=8
  • B4=8
  • B5=2
  • B6=10
  • BMUX=2
  • BQ=8
  • C4=8
  • C5=2
  • C6=10
  • CIN=8
  • CLK=8
  • CMUX=2
  • COUT=8
  • CQ=8
  • D4=8
  • D5=1
  • D6=9
  • DMUX=2
  • DQ=8
SLICEX
  • A=7
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=3
  • A6=10
  • AQ=3
  • B=3
  • B1=1
  • B2=1
  • B3=1
  • B4=2
  • B5=3
  • B6=4
  • BQ=1
  • C=1
  • C5=3
  • C6=4
  • CLK=3
  • CQ=3
  • D=3
  • D5=2
  • D6=5
  • DQ=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -i -p xc6slx100-fgg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 40 33 0 0 0 0 0
arwz 1 1 0 0 0 0 0
bitgen 81 77 0 0 0 0 0
bitinit 2 2 0 0 0 0 0
compxlib 22 22 0 0 0 0 0
cse_server 2 2 0 0 0 0 0
map 87 77 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 24 24 0 0 0 0 0
ngdbuild 88 88 0 0 0 0 0
obngc 6 6 0 0 0 0 0
par 77 77 0 0 0 0 0
platgen 14 5 0 0 0 0 0
trce 77 77 0 0 0 0 0
xps 39 16 0 0 0 0 0
xst 160 159 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 ) /doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=Modelsim-SE Mixed PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2021-05-31T16:39:08
PROP_intWbtProjectID=BD19ECB4BFF6419EA9562F423FC482C1 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_CompxlibEdkSimLib=false PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx100 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=fgg484 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_COREGEN=1 FILE_VERILOG=1
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=20.000 clkin2_period=20.000 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=1 primtype_sel=PLL_BASE
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=false use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=false use_power_down=false use_reset=false
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=41 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=14 NGDBUILD_NUM_LUT1=38 NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_LUT6=2 NGDBUILD_NUM_MUXCY=38 NGDBUILD_NUM_OBUF=13 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=40
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=41 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=14 NGDBUILD_NUM_LUT1=38 NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_LUT6=2 NGDBUILD_NUM_MUXCY=38 NGDBUILD_NUM_OBUF=13 NGDBUILD_NUM_PLL_ADV=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=40
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx100-3-fgg484
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5