Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
41 |
126,576 |
1% |
|
Number used as Flip Flops |
41 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
63 |
63,288 |
1% |
|
Number used as logic |
61 |
63,288 |
1% |
|
Number using O6 output only |
23 |
|
|
|
Number using O5 output only |
36 |
|
|
|
Number using O5 and O6 |
2 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
0 |
15,616 |
0% |
|
Number used exclusively as route-thrus |
2 |
|
|
|
Number with same-slice register load |
0 |
|
|
|
Number with same-slice carry load |
2 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
22 |
15,822 |
1% |
|
Number of MUXCYs used |
40 |
31,644 |
1% |
|
Number of LUT Flip Flop pairs used |
63 |
|
|
|
Number with an unused Flip Flop |
22 |
63 |
34% |
|
Number with an unused LUT |
0 |
63 |
0% |
|
Number of fully used LUT-FF pairs |
41 |
63 |
65% |
|
Number of unique control sets |
1 |
|
|
|
Number of slice register sites lost to control set restrictions |
7 |
126,576 |
1% |
|
Number of bonded IOBs |
14 |
326 |
4% |
|
Number of RAMB16BWERs |
0 |
268 |
0% |
|
Number of RAMB8BWERs |
0 |
536 |
0% |
|
Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2s |
1 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
1 |
16 |
6% |
|
Number used as BUFGs |
1 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
12 |
0% |
|
Number of ILOGIC2/ISERDES2s |
0 |
506 |
0% |
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
506 |
0% |
|
Number of OLOGIC2/OSERDES2s |
0 |
506 |
0% |
|
Number of BSCANs |
0 |
4 |
0% |
|
Number of BUFHs |
0 |
384 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
0 |
180 |
0% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
4 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
1 |
6 |
16% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
1.44 |
|
|
|