Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=Modelsim-SE Mixed |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2021-05-31T16:39:08 |
PROP_intWbtProjectID=BD19ECB4BFF6419EA9562F423FC482C1 |
PROP_intWbtProjectIteration=1 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_CompxlibEdkSimLib=false |
PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx100 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=fgg484 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=Verilog |
FILE_COREGEN=1 |
FILE_VERILOG=1 |