Simultaneous read/write with Quartus-|| single clock FIFOs

[AussieBruce]

I’m starting to use single clock FIFOs implemented under Quartus-II, implemented as megafunctions. I’ve read through the documentation, and can’t see any specific reference to the query I have, that is: Can writes and reads occur completely asynchronously, or must there be some user input to keep them separate in time?

My understanding of FIFOs is that their specific purpose is to allow, for example, reads and writes on the same clock cycle, but I want to be certain. That situation is going to occur from time to time with my application.

[jahonen]

Yes, it is ok to simultaneously read and write with a single clock FIFO. I think that is quite usual use case.

Regards,
Janne

[AndyC_772]

You certainly can both read and write on the same clock edge, no issue with that at all.

Do note that most, if not all, Intel / Altera FPGAs are unavailable to purchase through distribution right now, and have been for some time. Personally I'd be designing these parts out and migrating to a new vendor, unless this is a one-off hobby project, or you have some special arrangement with Intel to obtain a supply of parts.