Sine Wave on FPGA

[knight]

I want to make a sine wave using the approximation shown in this video,
I have an 8-bit phase accumulator which goes from 0 to 255 and then overflows. I want to use this 0-255 output and create the sine wave. Can anyone give an idea how to do it using the equations in the video?
Thanks

[woofy]

I have an 8-bit phase accumulator which goes from 0 to 255 and then overflows. I want to use this 0-255 output and create the sine wave. Can anyone give an idea how to do it using the equations in the video?
Thanks

If you have a RAM block available, use the output as an address to the RAM which will be loaded with a pre-calculated sine table.

[knight]

I have an 8-bit phase accumulator which goes from 0 to 255 and then overflows. I want to use this 0-255 output and create the sine wave. Can anyone give an idea how to do it using the equations in the video?
Thanks

If you have a RAM block available, use the output as an address to the RAM which will be loaded with a pre-calculated sine table.

I want to avoid using RAM as i plan to increase bit width of phase accumulator to 16 bits.

[emece67]

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[knight]

AFAIK there are 3 recent threads here about how to compute sine/cosine values in embedded, so I advice on looking for them.

There seem to be 4 basic approaches:

• Table lookup
• Polynomial approximations (with around 4 multiplications may be enough for you, using a 5rd order odd polynomial and Horner's scheme)
• The "state variable" method, useful to generate the next sample based on the previous one (not such useful in this case)
• The Bhaskara's formula (needs a division)

In your case, Bhaskara's is:

Code: [Select]

y = x*(128 - x)
sinx = 4*y/(20480 - y)

Valid for [0 <= x <= 128] (meaning 0-180º). You must manage the [128 < x < 256] case before applying the formula.

Regards.

For 128<x<256, it would be just the negative/complement of the original formula, right?

[emece67]

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[Berni]

The most efficient method for generating high resolution sine waves in hardware is CORDIC:
https://zipcpu.com/dsp/2017/08/30/cordic.html

This is commonly used as a way of generating sine wave signals in the digital world. But it is not quite all that simple to do.

Easier method that should still work well is a lookup table with interpolation between samples. If you stick to power of 2 numbers for your table size, then you can simplify the interpolation math down into just bitshit and addition operations. So it should be pretty compact and fast.

[SiliconWizard]

Using a table storing one period is definitely one easy approach and doesn't necessarily require a huge amount of samples. You just need to implement some interpolation on top of that, and the degree of interpolation + size of the table will determine your accuracy. A reasonably-sized table with even just linear interpolation is often more than good enough (but we know nothing about the OP's requirements.)

You don't need a lot of memory. Even a small FPGA with a few KBytes of EBR will absolutely do the trick. One thousand samples is plenty for most cases. But you need interpolation!
The benefit of the table-based approach with interpolation is that it can be reused for any kind of periodic signal, whereas implementations specific to sine functions will just generate sine waves. So unless you're VERY short on memory (like an ultra-small CPLD), I'll favor that.

The other approach is CORDIC as said above. Actually, the base idea is a rotation matrix, something that I also use in software for generating continuous sine waves (much faster, and usually more accurate than implementing an approximation of sin(x) for any x, when you only need successive values with a fixed step in x.)

[pcprogrammer]

When it is only a sine that is needed one can suffice with just a quarter sine in a lookup table.

See: https://www.fpga4fun.com/DDS.html

[ejeffrey]

I have an 8-bit phase accumulator which goes from 0 to 255 and then overflows. I want to use this 0-255 output and create the sine wave. Can anyone give an idea how to do it using the equations in the video?
Thanks

If you have a RAM block available, use the output as an address to the RAM which will be loaded with a pre-calculated sine table.

I want to avoid using RAM as i plan to increase bit width of phase accumulator to 16 bits.

You don't need the lookup table width to match your accumulator.  In fact it rarely does.  The accumulator width sets your frequency resolution while the lookup table width is normally close to your DAC resolution and contributes to spurs.  So a common approach is to have a 32-48 bit accumulator for very fine frequency resolution but only a 10-12 bit lookup table.

As mentioned your lookup table only needs to hold 1/4 cycle, the rest can be calculated from that.  Interpolation helps, a lot and dithering can spread out the spurs to make them less objectionable.

[BrianHG]

Unless you store your table in logic gates, careful that you do not needlessly over-minimize.

For example, Altera's M9K blockram has the smallest possible size of 1k X 8, or 256word x 32, or 512word x16. 

Each of these will utilize 1 block ram chunk.

Even if you think you are smart and say I will squeeze my quarter sine table into 64words by 8 bits, this will still consume the same 1 blockram chunk as making a table of 1024words by 8 bits, or 256words by 32 bits.  Only the extra bits are thrown in the garbage and cannot be used by any other HDL code.

[SiliconWizard]

Even if you think you are smart and say I will squeeze my quarter sine table into 64words by 8 bits, this will still consume the same 1 blockram chunk as making a table of 1024words by 8 bits, or 256words by 32 bits.  Only the extra bits are thrown in the garbage and cannot be used by any other HDL code.

Indeed.

[NorthGuy]

This is FPGA, so you don't need to use tricks to do things fast. With few pipelined DSPs you can calculate sine values with Taylor series at very high frequency. 400-500 MHz may be feasible. In reality, you don't really need it that fast.

You can use various tricks to optimize your caluclations, but this won't really make it faster, but rather save the area. That is your efforts will lead to using less DSPs, or less logic, but they will not lead to increased speed.

Thus, unless you're really concerned with using few extra DSPs, I would use Taylor series. Since you don't need high precision, you'll need only 2-3 members.

[emece67]

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[free_electron]

Using a table storing one period

you only need a quarter period. count up, count down, change sign, count up count down , change sign repeat ...

[BrianHG]

Using a table storing one period

you only need a quarter period. count up, count down, change sign, count up count down , change sign repeat ...

More like use the top 2 most significant bits of your position counter to decide the direction of addressing the table & if the output should be set to a negative value while all the least significant bits address your FPGA blockram.  At least with this, you can randomly jump to any angle within your sine table.

Then look at the minimum FPGA blockram size and strategically choose you final resolution of your sine table.

[hamster_nz]

I've added an new thread on how CORDIC works,, including a VHDL implementation.

Hopefully those interested find it of value.

CORDIC is really pretty neat, and can also be used to calculate atan2(y,x) and k*sqrt(x^2+y^2) too.