### Author Topic: SIPO shift reg circuit to verilog  (Read 1189 times)

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#### Daxxin

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##### SIPO shift reg circuit to verilog
« on: April 04, 2020, 09:34:44 am »
need to convert this schematic in verilog possibly for altera cpld who can help me pls

#### cruff

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##### Re: SIPO shift reg circuit to verilog
« Reply #1 on: April 04, 2020, 12:53:49 pm »
First step is to obtain the datasheet for the 4094 shift registers. Based on the description in the data sheet, implement an 8 bit shift register that matches the described behavior of the 4094, then hook them up with the appropriate connections.

#### TomS_

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##### Re: SIPO shift reg circuit to verilog
« Reply #2 on: April 06, 2020, 05:18:37 am »
need to convert this schematic in verilog possibly for altera cpld who can help me pls

There are many many examples of shift registers available on the Internet, and some even come as examples with the vendors software.

As a learning exercise it is always a good idea to try implementing something, and then ask for help if you get stuck. A shift register is stupidly easy to implement.

#### rstofer

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##### Re: SIPO shift reg circuit to verilog
« Reply #3 on: April 06, 2020, 05:09:09 pm »
Spend a lot of quality time with the datasheet: http://www.ti.com/lit/ds/symlink/cd4094b.pdf

Look at the Truth Table and note
1) regardless of the state of Strobe, output QS is set equal to Q7 on every rising edge of the clock - make this an always block on the rising edge of the clock

2) Note that QS' is set to Q7 on every falling edge of the clock - make this an always block on the falling edge of the clock

So far, we have covered lines 1,2,3, part of 5 and all of 6

3) Create an always block on rising edge of clock.  If strobe = 1 then Q <= Q[6 downto 0] & DataIn (sort of VHDL like, I don't do Verilog).  Basically, you are shifting the 7 least significant bits left and concatenating the incoming data bit whether 0 or 1.

NOTE:  We're going to get messed up here, bits are number 0..7 in the FPGA, not 1..8 so Q7 is actually Q[6], not Q[7].  I would rewrite the Truth Table using 0..7.  Be very careful!

You can forget about the OC (Open Circuit) conditions, you can't do 3 state logic inside an FPGA (generally), only on pins leaving the chip.  If the signals need to be MUXd on a bus, you will need to create a MUX or one will be inferred anyway.

The way I see this device is as 3 always blocks or perhaps a single always block with conditionals for either edge.  I think the 3 block solution is more intuitive but disjointed.

One block for QS, another for QS' and a final block for the shifter.

Something like this...

#### rstofer

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##### Re: SIPO shift reg circuit to verilog
« Reply #4 on: April 06, 2020, 05:13:48 pm »
Once you have a module for the CD4094, you just need to plunk down two instances, add in an inverter (a Verilog ~) and wire things together.

Smf