Soft CPU tools

[drwho9437]

I have used Quartus, ISE, Vivado, and Radiant for Cyclone, Spartan, Artix and Certus-NX targets. I started with VHDL, taught in systemVerilog and now use VHDL again. I have tended to do ultra low level projects with the FPGA mostly as glue/buffer. For work that mostly is what I would probably do going forward as well.

I'm interested however in doing more custom SoC stuff perhaps, and am interested in whom do you think offers the best tools to do SoC for free. Clearly everyone offers IP but I am looking for free. In the sort of we will give you the IP blocks and tools to sell Silicon space who seems the best? I cannot really justify 1000s for licenses.

My projects would be small anyway but rather than having a separate microcontoller it might be a BOM reduction to just have a softcore CPU in my FPGA fabric for some physical measurement system designs.

What do you think the most valuable features are?

[BrianHG]

For free and cross platform, try looking here:
https://opencores.org/projects
Look in processors.

You can also find projects on Github.

[asmi]

Xilinx offers a wide range of free IPs with their Vivado package, and that includes Microblaze softcore, which is free for any configuration (including the one with MMU which can run Linux, or even 64 bit version if that's what you want/need).

[nctnico]

I'd recommend to stay away from anything from Opencores. Most is mediocre at best. Where it comes to softcores, stick to the ones from the major FPGA vendors. I have used the LM32 core from Lattice in a couple of projects using a Xilinx FPGA. Works pretty well, is open source and portable. The portability helps to change FPGA vendors more easely.

[drwho9437]

I am well aware of open cores but don't feel it is very cohesive or documented for the most part. I am looking for good tool chains not put everything together from scratch. It might not be there for free, in which case I won't bother as an external hard-core is only 5-10 dollars more.

[BrianHG]

You can always write your own.
I made my own processor which has a assembler where I made 'op-code' and registers compatible with Microchip PIC series opcode + some added goodies.  Now I just use MPLAB and build my C projects to a source .asm, then take the .asm and compile it in my compiler.  Just note that I have only done the 8bit pic and 16bit ds-pics.  Also, some of the more embedded PIC hardware like I2C, UART, PWMs are my own home made peripherals.

[SiliconWizard]

My projects would be small anyway but rather than having a separate microcontoller it might be a BOM reduction to just have a softcore CPU in my FPGA fabric for some physical measurement system designs.

While this sentence shows you have already considered this point, I think it's worth considering some more before diving right into this CPU soft core approach, which, if you have no experience with it, is going to be a significant endeavor.

As to the BOM, except if you are already using a kinda beefy FPGA, the kind of soft core you're gonna be able to use (and associated memory from block RAM) will be pretty limited, and almost any small MCU for a couple bucks or less will beat that, with the ease of use you already are familiar with. Compared to the FPGA, the additional cost will be close to naught (unless you're using a very small and low-cost FPGA, in which case again the soft core you'll be able to use, if any, will be very very limited.) Then all that will really matter is possibly PCB area. Although one can find ridiculously small MCUs these days (like a few square mm in BGA.)

With that said, if you are really sure you want to go this path, you'll be tempted to either use a random soft core (as some have pointed out) that could be crappy and you'll spend days or weeks to debug it, or use a vendor-provided one (as some others have suggested), which will usually lock you in to a specific FPGA vendor. Which I don't particularly recommend especially these days of shortage.

So my suggestion would be to either use one of the proven RISC-V open-source cores (you can have a look at the Pulp platform for instance : https://www.pulp-platform.org/ ), or write your own as Brian said, but in that case, only if you have time to do it and any interest in doing it, as a more long-term project.

[nctnico]

OTOH there are several options to have an ARM or RISC-V core embedded in an FPGA. IIRC Gowin has several but they aren't the only ones.

[drwho9437]

My projects would be small anyway but rather than having a separate microcontoller it might be a BOM reduction to just have a softcore CPU in my FPGA fabric for some physical measurement system designs.

While this sentence shows you have already considered this point, I think it's worth considering some more before diving right into this CPU soft core approach, which, if you have no experience with it, is going to be a significant endeavor.

As to the BOM, except if you are already using a kinda beefy FPGA, the kind of soft core you're gonna be able to use (and associated memory from block RAM) will be pretty limited, and almost any small MCU for a couple bucks or less will beat that, with the ease of use you already are familiar with. Compared to the FPGA, the additional cost will be close to naught (unless you're using a very small and low-cost FPGA, in which case again the soft core you'll be able to use, if any, will be very very limited.) Then all that will really matter is possibly PCB area. Although one can find ridiculously small MCUs these days (like a few square mm in BGA.)

With that said, if you are really sure you want to go this path, you'll be tempted to either use a random soft core (as some have pointed out) that could be crappy and you'll spend days or weeks to debug it, or use a vendor-provided one (as some others have suggested), which will usually lock you in to a specific FPGA vendor. Which I don't particularly recommend especially these days of shortage.

So my suggestion would be to either use one of the proven RISC-V open-source cores (you can have a look at the Pulp platform for instance : https://www.pulp-platform.org/ ), or write your own as Brian said, but in that case, only if you have time to do it and any interest in doing it, as a more long-term project.

The Pulp thing looks pretty documented. I will look into it more. Lattice and Intel both are doing RISC-V also hopefully compilers are getting okay if that is an issue.

[DiTBho]

Opencores = crap
OpenRisc (especially the Allwinner's one) = crap ( full of bugs )

[DiTBho]

Risc-V & Gcc/binutils
MIPS32 & Gcc/binutils

[pbernardi]

You might take a look at DarkRiscV:

https://github.com/darklife/darkriscv
https://www.edaplayground.com/x/yiR

It is a small core (~1500LUT) under BSD license, so you can modify whatever you want, and has all the RISC-V tools benefits.

[laugensalm]

If you ask 'for free', rules are normally:
1) you only get what you don't pay for
2) you have to invest time yourself and adhere to opensource licenses

If you're looking for lean&mean low level and fully cycle accurate simulation of embedded software, I might throw in our legacy SoC builder system based on GHDL (thus, VHDL only):

https://github.com/hackfin/MaSoCist

There's a few CPU cores to choose from that focus on compactness. With some hacking into the kconfig setups, you can add your own.

WRT Opencores, I'd second the general opinion to stay away from most cores sitting in that repo.

[mr3141]

I've written a code generator that allows to couple GHDL with verilator. It doesn't allow full mixed language simulations, but verilog modules can be integrated in GHLD simulations.
https://github.com/miree/gvi

This is useful if you want to integrate a verilog-CPU into a VHDL-SoC and simulate with only open source tools.

[betocool]

Another one here:

https://www.neorv32.org/

This one's extremely well documented. I got it running in a few minutes.

Cheers,

Alberto