Electronics > FPGA

Soft CPU tools

<< < (3/3)

DiTBho:
Risc-V & Gcc/binutils
MIPS32 & Gcc/binutils

pbernardi:
You might take a look at DarkRiscV:

https://github.com/darklife/darkriscv
https://www.edaplayground.com/x/yiR

It is a small core (~1500LUT) under BSD license, so you can modify whatever you want, and has all the RISC-V tools benefits.

laugensalm:
If you ask 'for free', rules are normally:
1) you only get what you don't pay for
2) you have to invest time yourself and adhere to opensource licenses

If you're looking for lean&mean low level and fully cycle accurate simulation of embedded software, I might throw in our legacy SoC builder system based on GHDL (thus, VHDL only):

https://github.com/hackfin/MaSoCist

There's a few CPU cores to choose from that focus on compactness. With some hacking into the kconfig setups, you can add your own.

WRT Opencores, I'd second the general opinion to stay away from most cores sitting in that repo.

mr3141:
I've written a code generator that allows to couple GHDL with verilator. It doesn't allow full mixed language simulations, but verilog modules can be integrated in GHLD simulations.
https://github.com/miree/gvi

This is useful if you want to integrate a verilog-CPU into a VHDL-SoC and simulate with only open source tools.

betocool:
Another one here:

https://www.neorv32.org/

This one's extremely well documented. I got it running in a few minutes.

Cheers,

Alberto

Navigation

[0] Message Index

[*] Previous page