softcore: getting started

[prophoss]

A while back i had decided that I wanted to create a softcore on my FPGA. I did not know what all I would need to do to get it going. After I took a class on the microcontroller architecture I began to realize how much was actually involved. I now understand more about how to build a basic architecture and how it works. There is still a good bit I don't understand though and I still want to give it a try. Is there a good place to simulate this kind of thing online or would I need to build it on my FPGA? I am interested in using the RISC ISA but I am OK with using something else. I want to do a little learning by doing.
Thanks, Brian

[Omega Glory]

I would first figure out which ISA you are going to use. I recently made a softcore and in my opinion the ISA design was the most difficult part. This is because the way you encode your instructions effects how efficiently your control can decode the instructions, and this has critical path implications. Additionally I found it difficult to anticipate which instructions would be the most critical for writing simple programs. If you decide to design your own ISA, I suggest you look at different examples for inspiration (I looked at the AVR, MIPS, and 8085 ISAs).

I would 100% recommend that you first design and debug your HDL before putting it on an FPGA. I used Verilog for my design and used Icarus Verilog for simulation, and Scansion for viewing waveforms. You could also do simulation online in EDA Playground. If you don't do simulation, your design will probably not work and you won't have a good way of debugging it.

After you get your softcore working, you will need to write programs for it. It will quickly become a pain to write software in hex, so you will probably want to write an assembler to translate your source to machine code. You could also use an ISA that already exists, and then you'll get assemblers and compilers for free.

One last suggestion, if you are working on a custom softcore microcontroller, I suggest you also think carefully about how you're going to handle interrupts.

This is the softcore I've been working on: https://github.com/ept221/tinySoC, maybe you can get some ideas about what you want to do or avoid from it.

[asmi]

I recommend anyone to go with RISC-V ISA. It's very simple yet fully-featured, and you can use gcc to write programs for it using C as opposed to assembly (which is a BIG advantage in my book!). Also it's command encoding was designed for easy implementation and it has no legacy garbage, which tends to litter older ISA. And the cool thing is that once you have the base command set (RV32I) ready and working, you can slowly add other command subsets, all while retaining compiler support for these commands. So it's easy to start small and then grow once you have the basics down.
Oh, and forget about hardware until you have your CPU verified in simulation while running your firmware. You can use vendor's simulators if they provide one - I'm using Vivado simulator which is a part of their Vivado IDE for FPGA design.

[ejeffrey]

You can certainly do core design entirely in simulation, although if you eventually want to load it onto an FPGA it may help to have some idea which one so you are working with the right toolchain.  A core itself should be fairly portable but the tools will have different ways to define and interface with memory and other resources.

[asmi]

A core itself should be fairly portable but the tools will have different ways to define and interface with memory and other resources.

Most more-or-less modern FPGAs will have enough internal memory for typical softcore designs, and IDEs typically are pretty good at inferring memory from generic vendor-agnostic HDL description. Same goes for I/O - you can make typical GPIO module without using any hardware-specific components. So you can make this whole thing portable, unless you will be aiming to push the limits of performance and will have to do device-specific optimizations.

[SiliconWizard]

A core itself should be fairly portable but the tools will have different ways to define and interface with memory and other resources.

Most more-or-less modern FPGAs will have enough internal memory for typical softcore designs, and IDEs typically are pretty good at inferring memory from generic vendor-agnostic HDL description. Same goes for I/O - you can make typical GPIO module without using any hardware-specific components. So you can make this whole thing portable, unless you will be aiming to push the limits of performance and will have to do device-specific optimizations.

Yep.
And I too strongly suggest starting with embedded block RAM for instruction and data memory. Will be much easier to design and get right than trying to mess with memory controllers and caches. One thing at a time.

[BrianHG]

A core itself should be fairly portable but the tools will have different ways to define and interface with memory and other resources.

Most more-or-less modern FPGAs will have enough internal memory for typical softcore designs, and IDEs typically are pretty good at inferring memory from generic vendor-agnostic HDL description. Same goes for I/O - you can make typical GPIO module without using any hardware-specific components. So you can make this whole thing portable, unless you will be aiming to push the limits of performance and will have to do device-specific optimizations.

Yep.
And I too strongly suggest starting with embedded block RAM for instruction and data memory. Will be much easier to design and get right than trying to mess with memory controllers and caches. One thing at a time.

Most of my designs to date have a micro-home made OS sitting in block-ram, initialized from the bootprom.  I make sure there is enough code in there for RS232 debug port and basic setup & diagnostic capabilities for the rest of the design which wont be engaged unless everything checks out.

Having a SD-Card reader fitting into this block-ram code is also a plus for executing larger code.  Speed here isn't important, it's basic debug capabilities and a guaranteed error free initialization block which you can remotely stop or control/monitor the rest of the hardware before doing the main system booting.

[prophoss]

So, upon reading the replies you can use EDAplaygorund, and or vivado? I have used EDAplayground before but would have never figured you could do something so complicated there. Vivado is simply the xilinx provided way to program their FPGAs. I use or have used Quartis 2 since I have a cyclone4 chip. I have also used modelsim as well. Could I use that too? As far as an ISA goes I would be quite happy using RISC-V. I guess I am just trying to figure out how to implement that for use in a simulator since that is a possibility. Sorry for the delay in my reply, and thanks for the info.

[SiliconWizard]

Vivado has its own simulator: https://www.xilinx.com/products/design-tools/vivado/simulator.html
it works fine.

If you're using VHDL, GHDL is a good open-source simulator too. I use it very often. It's actively maintained.

[SMB784]

Vivado has its own simulator: https://www.xilinx.com/products/design-tools/vivado/simulator.html
it works fine.

If you're using VHDL, GHDL is a good open-source simulator too. I use it very often. It's actively maintained.

If you are looking for a good open source Verilog simulator, consider Verilator.  It is also actively maintained, and extremely helpful.

[rstofer]

A while back i had decided that I wanted to create a softcore on my FPGA. I did not know what all I would need to do to get it going. After I took a class on the microcontroller architecture I began to realize how much was actually involved. I now understand more about how to build a basic architecture and how it works. There is still a good bit I don't understand though and I still want to give it a try. Is there a good place to simulate this kind of thing online or would I need to build it on my FPGA? I am interested in using the RISC ISA but I am OK with using something else. I want to do a little learning by doing.
Thanks, Brian

There are lots of soft cores at OpenCores.org.

I really like the entire LC3 project because it is used at many universities for an undergrad computer architecture class.

https://www.eevblog.com/forum/fpga/fpga-avtive-open-source-projects/msg3382296/#msg3382296

You can find the appendices on the web and these have all the information you need.  You could buy the book but it is now very expensive.  I didn't pay anywhere near that kind of money.

The latest edition is not the one I used.  I used the second edition and I haven't looked to see how the third edition has changed.  I am aware of a newer project LC3b that uses byte addressing.  I guess if I could find all the appendices I could convert my project but I just don't have much interest in doing that.

https://www.alibris.com/Introduction-to-Computing-Systems-From-Bits-and-Gates-to-C-C-Beyond-Yale-N-Patt/book/42539098

https://justinmeiners.github.io/lc3-vm/supplies/lc3-isa.pdf

http://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/docs/LC3-uArch-PPappendC.pdf

There's no way in hell I would recommend a RISC-V processor for a first attempt.  OTOH, Hamster_nz's project is very nicely done.