DDR3 Strobe to data timing constrains

[ddr_controller]

I don't see in the ddr3 docs from Micron where are the timing constraints between DQS and DQ. I read somewhere that DQ should center align to DQS but did not find where that is said in the Micron datasheet, nor did I find the allowed jitter. Does anyone know where this spec is?

[BrianHG]

Read the full datasheet, it is there.  And it is also within a few pages of the DDR_CK/CK# to command tolerances.

[ddr_controller]

I really can´t find it, neither in the dc ac tables nor in the write section timing diagrams :/

[asmi]

I really can´t find it, neither in the dc ac tables nor in the write section timing diagrams :/

Maybe you should read again.
Read:


Write: