I'm encountering yet another Spartan-6 mystery... Bringing up my first self-designed FPGA board, after various earlier projects which used off-the-shelf boards from Numato. I can configure it nicely via JTAG, using the iMPACT software. iMPACT also states that indirect programming of an attached SPI flash ROM is successful. (Although it makes me slightly suspicious that the progress indicator only goes up to 25% during the programming; is that normal behavior?)
But the FPGA is not able to configure itself from flash when I power-cycle it; DONE won't go high. Looking at the CCLK and data lines with a scope, I see that there is plausible traffic -- but the CCLK, after about 800 cycles at 1 MHz, switches up to 50 MHz!
I don't think I asked for that; please see the Bitgen settings in the attached screenshot. Any idea what is happening here?
Signal integrity is often mentioned as a likely culprit for configuration issues. I have indeed omitted any termination resistors on the CCLK and data lines, due to space contraints. But this is a very compact layout, with a 15 mm long CCLK trace and < 20 mm data traces. The signals look perfect at the slow 1 MHz rate, and even seem to keep up at 50 MHz. Adding improvised kind-of-termination resistors to the CCLK and flash data output lines doesn't change anything either. So I don't think compromised signal integrity is the cause.
The behaviour is fully reproducible, always occuring at the same time (after about 800 µs of 1 MHz clock pulses), and on two separate boards I have populated. I assume the 800 µs time is when the FPGA is meant to switch from its conservative startup CCLK (is that expected to be 1 MHz?) to the clock rate defined in the Bitgen properties. But where does it get the idea to select 50 MHz?!
Many thanks for your ideas!
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