SQRL Acorn as an interesting Artix-7 board?

[apshamilton]

I am selling some Acorn 215s - new, unused but open box. Price is $70 for payment in crypto of $80 for payment via other methods.

See details here: https://www.hivelist.org/fpga/@apshamilton/acorn-215-xilinx-artix-7-200t-fpga-with-1gb-dram-usdus70-with-payment-in-crypto

[fanoush]

Got jtag working (thanks again Fred27 for the cable!), can see fpga  in xc3sprog however I did not find bitstream that would make SPI flash accessible, the bscan_spi_xc7v2000t.bit one here https://github.com/quartiq/bscan_spi_bitstreams does not work so there is more to it - probably needs to be specific for the board.

Also the fan is quite loud.  Does the FPGA  has some thermal protection built in? The heatsink is massive so I guess fan is not needed for moderate usage.

[asmi]

  Does the FPGA  has some thermal protection built in? The heatsink is massive so I guess fan is not needed for moderate usage.

No it does not. At least I've seen several times FPGA die temperature going beyond its' grade limit and it continued working. Current consumption increases with temperature, which can cause thermal runaway (higher current -> higher heating -> higher current and the loop closes), so I recommend to be very careful with FPGA thermal management.
If fan is annoying, maybe there is a way to modify the board so that it would only turn on once heatsink goes above certain temperature? Or maybe even PWM the fan speed to reduce the noise when possible.

[miken]

however I did not find bitstream that would make SPI flash accessible, the bscan_spi_xc7v2000t.bit one here https://github.com/quartiq/bscan_spi_bitstreams does not work so there is more to it - probably needs to be specific for the board.

I've not used the software in question but I think you want the xc7a200t file. For Xilinx FPGAs the SPI pins involved in configuration are fixed, so I don't think it would be board dependent.

As for noise, I soldered a somewhat larger fan to the carrier board but haven't figured the rest out yet.

[kentfielddude]

LCSC has the artix-7 200T for $90 usd
https://lcsc.com/product-detail/New-Arrivals_XILINX-XC7A200T-2FBG484I_C494680.html

[-gb-]

Greetings,
has anyone tried powering the Board through the Fan Connector?
Which modelnumber is the Fan connector or are there crimped cabled to buy?
And ... are there already crimped cables for the high-pincount-connector? How hard is it to do the crimping on your own?
How much power will be drawn without mining, just a minimal PCIe system?

What do i want to try?
There are Thunderbolt3 Cases für externals SSDs which have an M.2 inside. I want to install the FPGA Card in such a case, but there is no room for Fan or passive cooling. But i do not mine, i just want to test the bandwidth i can gat over Thunderbolt3. Theoretically, Thunderbolt3 is limited at 22 GBit/s, because 18 GBit/s are fixed reserve for Displayport (will change with Thunderbolt4). But the Artix7 only supports PCIe gen2 x4, that is 4x 5 GBit/s = 20 GBit/s.
(With Thunderbolt4, the limit is PCIe gen3 x4 = 32 GBit/s.)

Thank you!

[Foxxz]

What do i want to try?
There are Thunderbolt3 Cases für externals SSDs which have an M.2 inside. I want to install the FPGA Card in such a case, but there is no room for Fan or passive cooling. But i do not mine, i just want to test the bandwidth i can gat over Thunderbolt3. Theoretically, Thunderbolt3 is limited at 22 GBit/s, because 18 GBit/s are fixed reserve for Displayport (will change with Thunderbolt4). But the Artix7 only supports PCIe gen2 x4, that is 4x 5 GBit/s = 20 GBit/s.
(With Thunderbolt4, the limit is PCIe gen3 x4 = 32 GBit/s.)

Thank you!

I used this one with the NiteFury
https://www.amazon.com/gp/product/B07N74VZKZ/

The FPGA lights up and I THINK an unknown device shows up on 'lspci'.
You have to use the command 'boltctl' the first time you hook it up to authorize the device to connect to the system. I think its a security protection to prevent unknown devices from being plugged in since thunderbolt has DMA access.

[-gb-]

Greetings!
I did not jet try the Thunderbolt Case, but i received the FPGA board and indeed, the Fan is very loud. So i wrote a minimal VHDL project, just a counter for blinking LEDs and flashed it. The board consumes 60 mA @ 12 V, 12 V because i use the SQRL PCIe to M.2 adapterboard. Oh by the way, the DCDC regulator on this board is whining.
But now, the FPGA stays cool, even without cooling. I removed the heatsink with hot air.

Next i will read about PCIe and what to do to transmit data from FPGA to PC.

[SMB784]

After reading through the thread, it is my understanding that the 6 "I/O" pins broken out through the Pico EZMate connector are also broken out through the 20-pin Hirose DF52 connector.  Is this correct?  Also, are the JTAG pins broken out through the Hirose DF52 connector in addition to the Pico EZMate connector? 

[-gb-]

Is this correct?

Yes

Also, are the JTAG pins broken out through the Hirose DF52 connector in addition to the Pico EZMate connector?

No

https://raw.githubusercontent.com/RHSResearchLLC/NiteFury-and-LiteFury/master/Hardware/uEVB.pdf

[SMB784]

I don't know if you can safely short the VIN to the VOUT on U11 and get 3.3V out on the IO pins for the DF52 connector.  From the schematic, the 2.5V output of the U11 regulator also powers VDD of the 200 MHz RAM clock in addition to the 12 digital IO pins on the DF52 connector.  Maybe someone can check me on that; The datasheet for the oscillator (ASDMPLV-200MHz) says that VDD for this oscillator is between 2.25 & 3.6, so maybe 3.3V is no big deal for the RAM clock, but will the oscillator output increase as a result of the higher VDD and possibly harm the clock input pins on the FPGA?  I also worry about noise on the unregulated 3.3V line affecting the oscillator that used to be powered by a 2.5V regulator.   Someone else ought to weigh in on that too.

[SMB784]

I looked up the recommended input voltages from the datasheet for the XC7A200T (see attached image), and it says that the max safe input for the differential IO banks is ~2.6V, meanwhile the datasheet for the oscillator says that for VDD between 2.2 & 3.6V the oscillator output swings by 0.35V and has an offset of 1.5V, which leads me to believe that the oscillator has a peak voltage of somewhere between 1.5 and 1.85V.  This is within the voltage input spec of the FPGA pins, but someone with more hardware knowledge should check my reasoning here.

[-gb-]

The voltage swing of the LVDS OSC is not the limit of the bank voltage. This is a HR bank, VCCO can be set up to 3.6 V, see https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf . So 3.3 V is fine.
BUT:
With 3.3 V VCCO you cannot use this bank to output LVDS. (LVDS input works fine). If you neet to output an differential signal with 3.3 V VCCO, you may use
IOSTANDARD TMDS_33
as it is used for HDMI.

[SMB784]

The voltage swing of the LVDS OSC is not the limit of the bank voltage. This is a HR bank, VCCO can be set up to 3.6 V, see https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf . So 3.3 V is fine.
BUT:
With 3.3 V VCCO you cannot use this bank to output LVDS. (LVDS input works fine). If you neet to output an differential signal with 3.3 V VCCO, you may use
IOSTANDARD TMDS_33
as it is used for HDMI.

I think we are talking about different things here. It has been proposed that you can change the output of the pins on the DF52  connector from 2.5V to 3.3V by removing the 2.5V regulator (U11) and shorting the U11 pads corresponding to Vin and Vout.

The problem with that is that regulator is not just driving those DF52 pins, it's also serving as VDD for the 200MHz RAM clock oscillator chip (X1). My fear is that when changing VDD for that chip by swapping the 2.5V U11 regulator with a short to 3.3V, the output of the X1 oscillator will become too high voltage for differential the input pins that it is connected to on the Arty-7 FPGA.

According to the datasheet, these pins can only handle at most 2.6V, which may be lower than the output voltage if the X1 oscillator at its new 3.3V VDD.

However, if the output of the X1 oscillator remains below 2.6V despite the higher VDD, then this isn't a problem, and the only concern is line noise on the unregulated 3.3V rail interfering with the oscillator output. That may not be a problem either though, given that the oscillator has 50dB of rail isolation

[-gb-]

Sorry!

But ... look at the datasheet: https://abracon.com/Oscillators/ASDMP.pdf Minimum Supply Voltage is +2.25 V. So the LVDS OSC will work fine.

[SMB784]

Sorry!

But ... look at the datasheet: https://abracon.com/Oscillators/ASDMP.pdf Minimum Supply Voltage is +2.25 V. So the LVDS OSC will work fine.

Thanks, I'm pretty sure the oscillator will work fine, my concern is about the oscillator output.  Does the output of the oscillator change as a function of the input voltage VDD?  The Datasheet entry for the CMOS version of this oscillator says that it does, but the entry for our oscillator (LVDS variety) doesn't seem to say very much about how the output voltage is affected by VDD.  If the oscillator output rises above 2.6V as a result of the higher VDD, it can damage the input pins on the FPGA.

[-gb-]

Ah OK. This OSC outputs LVDS. Both pins swing 350 mV around a DC level of 1.125 V ... 1.4 V. So they are far below the 2.5 V.

[SMB784]

Ah OK. This OSC outputs LVDS. Both pins swing 350 mV around a DC level of 1.125 V ... 1.4 V. So they are far below the 2.5 V.

Do you think that output is unaffected by the VDD? I don't see anything in the datasheet indicating that the output changes as a function of VDD, but I don't see anything saying that it doesn't either.  My guess is that if it was affected by VDD, they would probably say so like they did with the CMOS variant, but I'm not familiar enough with industry practices to know whether this omission was intentional (indicating that there is no dependence on VDD) or just the result of a poorly specified datasheet.

[-gb-]

Do you think that output is unaffected by the VDD?

Yes. It is LVDS.

[SMB784]

Do you think that output is unaffected by the VDD?

Yes. It is LVDS.

Gotcha, thanks for the reassurance.

For those of you who are trying to put together the DF52 cable, I recommend that you don't actually try to assemble it from the connector, crimp terminal, & wires.  This is a fools errand unless you have the $6000 specialized crimping tool and the appropriate kind of wire.  I recommend that you just buy the cables pre-crimped for insertion into the DF52 housing.   Those cables can be found on mouser (link here). For 20 of them + the DF52 housing it will cost you about $25 without shipping.  Digikey only sells them in batches of 100, which will cost you about $57 + shipping.

[SMB784]

Hey everyone,

I wrote a minimal hardware configuration that blinks all the accessible LEDs and outputs square waves of different frequencies on all 12 of the GPIO outputs on the DF52 board.  This might be useful for people to test whether or not their board works after they get it.  The vivado project can be built by cloning my github repository (found here https://github.com/SMB784/SQRL) and using the TCL script build_SQRL.tcl.  The github repository also includes instructions on how to program this board using a generic FT232H to USB adapter rather than the usual special Xilinx cable, as well as automatic scripts for uploading the post-implementation SQRL_top.bit & SQRL_top.bin files for programming the FPGA and the flash.

In order to get 3.3V output on DF52 pins 15, 16, 18, and 19, you are required to remove the U11 regulator and short the input and output pins on the U11 pad together, as described earlier in this thread.  I have confirmed that this works, and does not negatively affect the board in any way that I have noticed.

I have attached images of the waveform output from pin 3 (3.3V GPIO pin at 12.5 MHz output) and pin 19 (2.5V LVDS pin modified to 3.3V GPIO at 6.1 kHz output ) to this post.

If you need to put together a DF52 cable, I highly recommend getting the specific DF52 cables with the pre-crimped ends (found here on Mouser) that fit into the DF52 housing (found here).  Cutting the cables in half will allow you to make 2 DF52-to-whatever-you-want cables (in my case, IDC20 connectors).

Hopefully this helps someone else make good use of this board 

[SMB784]

Having tested this basic load out, the SQRL Acorn 215/215+ board appears to be a pretty good dev board for the money.  You get the best available 7 Series FPGA (Artix7 200T) that can be programmed with Xilinx's free tools, and you have the option to have it with the top speed grade (if you get the 215+).  This dev board has 12 GPIOs operating at 3.3V, 4 user controllable LEDs, an M.2 adapter for a PCIe interface with even more pins, and an easy to access JTAG port for configuration/programming.  Overall this is a pretty great deal for <$100.

[teslabit77]

Hello folks..

I'm looking for buy ONE(1) High-Power M.2 PCIe x4 adapter for acorn 215.

please let me know if anyone have this PCIe board.


Danny.

[asmi]

You get the best available FPGA (Artix7 200T) that can be programmed with Xilinx's free tools, and you have the option to have it with the top speed grade (if you get the 215+). 

This is not even close to being true. There are much better FPGA available in free license.

[SMB784]

You get the best available FPGA (Artix7 200T) that can be programmed with Xilinx's free tools, and you have the option to have it with the top speed grade (if you get the 215+). 

This is not even close to being true. There are much better FPGA available in free license.

You're right! The UltraScale/UltraScale+ FPGAs apparently now work with the free Vivado webpack: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture

So, if you are ready to throw down thousands of dollars for your learner's dev board, then you will get way more power than you could muster with this ~$60 board.

Of course that would be rather ridiculous to even suggest, given that the entire premise of this thread involves repurposing a bitcoin FPGA for less than a hundred dollars. Nevertheless, I have sightly modified my post to reflect this trivial fact.

EDIT: For a list of dev boards for FPGA with better specs (and associated price) than the Artix7 200T which can be programmed by the free tools, see below:

AVNet Ultrazed-EV (XCZU7EV for $999)
Kintex UltraScale+ FPGA KCU116 Evaluation Kit (XCKU5P $2995)
Trenz TE0803 (XCZU5EV $1200)
Trenz TE0807 (XCZU7EV $1830)

As you can see, these boards have better specs but are more than 10 times more expensive.  Other boards either can only be programmed with  tools that cost more than 10 times the price of this Arty7 board, or can be programmed with free tools but are themselves more than 10 times more expensive than this Arty7 board.

With this SQRL Acorn board, you are getting an extremely good FPGA for rock bottom prices, and you still get 12 good GPIO ports, external JTAG access, and PCIe as well all for only $60-$80.