SQRL Acorn as an interesting Artix-7 board?

[miken]

Oh wow the Acorn does look like a NiteFury. They probably changed as little as possible.

The FPGA speed/temp grade are supposed to be in the 2D barcode on the die. It looks like the guy who did the video didn't clean all the gunk off though.

[Fred27]

Thanks to richardbb discovering the NiteFury, I decided that I'd take a punt. I managed to get one for £30. I expect that it will indeed be unlikely to get to a point of it being vaguely useful, but the journey to nowhere might be fun.

[miken]

Should be fun There are four same-bank LVDS pairs on the Hirose connector, so I'm going to look at designing an HDMI dongle. And an adapter for the Xilinx pod.

So I'm puzzling over the timeline of Acorn and NiteFury. The first post about the Acorn on bitcointalk was June 1, 2018. The crowdfunding campaign for NiteFury began on March 12, 2019. From what I can tell, people were receiving Acorns by the end of 2018. From these dates it would appear that NiteFury came out of the Acorn project and not the other way around. I wonder what the story is there.

https://bitcointalk.org/index.php?topic=4391318.0
https://www.crowdsupply.com/rhs-research/nitefury/updates/crowdfunding-has-begun

[conmega]

So I just nabbed some of these and in doing my own research Nitefury says this in a lot of their materials:

Affordable: Buying the Xilinx Artix-7 XC7A200T FPGA alone would generally cost around $250. By teaming up with another company, NiteFury gives you all that power with little additional cost (especially during the campaign).

So I think SQRL and RHS Research were working together on this but I guess neither publicly state it.

Either way I am curious to see what the speed grade on these are... I got refused access to Xilinx's 2D barcode decoder... I did end up drawing up what the barcode was in that guy's video but the data is useless without this decoder from Xilinx... I may apply for it through my place of work and see if I can throw it through there.
Nitefury apparently offered speed grade 3 parts for the first 100 parts shipped. But I have YET to see what the default speed grade they would ship after that so its a bit of a toss up...
Real shame there is no way to check speed-grade over JTAG... You'd think this would be the best protection from preventing people from re-badging parts... Instead of locking an encoded barcode decoder behind a corporate wall.

[OwO]

I think I still have access to the barcode thing; was also denied the first time but after using a friend's corporate email address they approved it. You can DM me the barcode or post it here. They used to have a web interface to look up device info using device DNA (which can be read through JTAG) but it seems to be gone and only the app remains.

[conmega]

Thanks that would avoid the headache of applying with my work address and waiting the day or two! Attached should be a faithful recreation of the 2D Barcode off the chip shown in the video mentioned further back in the thread.
It at-least decoded with an online 2D Barcode decoder.

If Xilinx has no idea what it is let me know and I'll have to look at it more closely.
I will also get a good photo of the one on one of the acorns I get when I get them but that will be a few days.
[attach=1]

[conmega]

So for anyone with these to make up a JTAG cable Digikey sells pre-made cables for the Molex Pico-EZ connectors on the board.
https://www.digikey.com/product-detail/en/molex/0369200601/WM26622-ND/10233018
Quite reasonable considering you can cut it in half and have the connectors for both the 4 multi-purpose I/O and the JTAG header.
Although TO NOTE the 4 general purpose I/O on the Pico-EZ connectors are mirrored as the "4 multi-purpose" on the 20 pin Hirose DF52 connector... So slightly less I/O available...
But I was looking at the schematics:
https://github.com/RHSResearchLLC/NiteFury/blob/master/Hardware/uEVB.pdf

Notice the PCIE_DIO and the SMBUS both go to general I/O on the FPGA, as would make sense.
So IF your not going to use these in a computer... And just on the bench... Those are also available as I/O...
So that's 6 pins there. Might be-able to still use PCIe and get those pins usable with a custom board just not in a standard PC anyway where it may expect SMBUS.
Though SQRL also made PCIe to M.2 boards with PLX chips on them and that has an "m.2 SMBUS enable" switch so...?
Either way seems like total usable pins from the FPGA so far are:
4 LVDS 2.5V pairs, 4 3.3V General purpose I/Os (also two pairs so you can do 2 more LVDS with that if you want), 6 I/O pins on the M.2, 4 PCIe RX/TX pairs and the Refclock pair.

Also NiteFury mentions they would ship speed grade 2 parts on normal boards... So that MAY be what Acorn would ship. Would make sense to bulk order one part for the lower price point.
Considering they sold a CLE-215 and a CLE-215+ and their cooling solution is beefier than the nitefury part though... May be that the 215 is a SG 2 and the 215+ is a SG 3. Purely speculation though.
I am going to guess SG 2 worst case scenario though.

[Fred27]

I bought the same Pico-EZ cables (although slightly longer) and I'm hoping to see if I can get JTAG working this weekend.

I don't think the strength of this board will be externally available I/O, but if between us we can get PCIe working. I'm hoping the Nitefury example will be helpful.

[OwO]

I had to add some white border to that barcode before it will scan, but here is the result:

[conmega]

Getting PCIe working should be little issue
Pretty much just dropping the IP block in and hooking to it via AXI.
Now what you want to do with it after that and interfacing with AXI is the part that gets fun.
Here is an example of another product and a nice little write-up on getting a basic PCIe IP block dropped in and actually seeing it on a system its plugged into.
https://numato.com/kb/getting-started-with-pci-express-on-nereid/

I had to add some white border to that barcode before it will scan, but here is the result:

Woot! Fantastic to see. So long as I didn't mangle that barcode when re-creating it we should hopefully have just ensured that the these CLE-215+ parts are in-fact speed grade 3.
So probably a safe assumption the CLE-215 is speed grade 2 and the CLE-101 is just a XC7A100T something.
Some of the best Virtex parts available! Don't know what the E means... Maybe the temp code which would be Extended in that case, 0-100C.

I also just ordered up some cables, missed further back in the thread the P/N for the 300mm ones so I ordered those up, probably best to not get 100mm, probably a tad bit too short
I am also going to try my hand at hand crimping some of the itty bitty Hirose connectors... Got 5 housings and 100 pins for like... 5 bucks or whatever... Figured its worth a shot.

Looks like my boards should arrive next week.

[Fred27]

I also got some Hirose connectors. The look like they will be tricky to crimp. I might have to do it under a microscope!

The Pico-EZ also surprised me. I thought they would slide in sideways, but you have t push them straight down to click into place.

[Fred27]

Some initial success! It seems the JTAG connector matched the pinout on the uEVB schematic. That's the smaller brother of the NiteFury. (Sorry, the PicoEVB is the smaller one. The uEVB must be another name for the NiteFury.)

[attachimg=1]
I can detect the Artix-7 in Vivado. I'm using a Digilent HS2 and an adapter hacked together out of bits from one of those fake Xilinx programmers on eBay. The board is powered by the 12V power input on the PCIe adapter.

For reference the JTAG pinout is (starting furthest from the I/O port and working towards it)
1 GND
2 TCK
3 TDO
4 TMS
5 TDI
6 3V3

This gives me more confidence that the Nitefury and SQRL Acorn may share a lot.

[miken]

That's great news
Yesterday I hooked up a cut-in-half Pico-EZmate cable and then realized I had no convenient way of hooking up the Xilinx dongle to it. If it cools down enough tonight perhaps I will break out the soldering iron.

Also great news about the speed/temp grade. Yeah, E should be Extended. Thanks for getting that info, guys.

The layout of the PCIe lanes is kind of inconvenient in this design since Xilinx has one blessed lane order. I prefer to regenerate Vivado projects from TCL scripts so I'm looking at finding a sufficiently elegant way of modifying the xdc constraints inside the IP on project creation. I think taking the IP out of managed mode and doing some hacky TCL find/replace should work.

[Fred27]

The NiteFury sample project does something funky with constraints regarding PCIe. The details were lost on me, but it might mean something if you're familiar with PICe stuff. See build notes here: https://github.com/RHSResearchLLC/NiteFury/tree/master/Sample-Projects/Project-0/FPGA-A200T-3. I can successfully run this project via JTAG and some different LEDs blink. Not pushed to flash, so it goes back to whatever is on flash when restarted - some mining algorithm I expect.

I need to put this down and get on with some work for a bit, but good to know the Artix-7 is reachable. This is my simple setup at the moment - powering the board via a Molex MiniFit in place of a PCIe power cable and a quickly solder adapter hack for the JTAG. Next step will be verifying that the connectors are laid out as expected. No benefit in putting it inside a PCIe slot just yet.
[attach=1]

[conmega]

The NiteFury sample project does something funky with constraints regarding PCIe. The details were lost on me, but it might mean something if you're familiar with PICe stuff. See build notes here: https://github.com/RHSResearchLLC/NiteFury/tree/master/Sample-Projects/Project-0/FPGA-A200T-3. I can successfully run this project via JTAG and some different LEDs blink. Not pushed to flash, so it goes back to whatever is on flash when restarted - some mining algorithm I expect.

I need to put this down and get on with some work for a bit, but good to know the Artix-7 is reachable. This is my simple setup at the moment - powering the board via a Molex MiniFit in place of a PCIe power cable and a quickly solder adapter hack for the JTAG. Next step will be verifying that the connectors are laid out as expected. No benefit in putting it inside a PCIe slot just yet.
[attach=1]

You will NEED at-least a 100Mhz PCIe ref-clock if your going to run the example design from Nitefury.
I have been playing around with examining the Nitefury example and also setting up a project with a RiscV core generated out of their ChipYard project with the ultimate goal to have not only DDR3 but PCIe host off it.
The limitation is that there is only one on-board clock on the NiteFury/Acorn, a 200Mhz DDR clock. Theoretically you can use that DDR clock for other stuff internally and even to generate the 100Mhz PCIe clock if your going to say run PCIe in host mode and want to spit out a 100Mhz ref. But its a bit of a learning curve where you can use the internal buffers and where you can't.
But right now it seems easiest to just say get a cheap x1 PCIe riser and plug that into the little breakout board you have to get a 100Mhz ref clock from a system.

If you get the example project open in the design view where it shows you the blocks and how they interconnect it should become clearer to you what blinking LEDs mean what and what clocks are required for what.
I believe one blinks to indicate DDR train complete. The other should be PCIe Link train complete I think.

Also you'll probably want some connection to a PC for the NiteFury example since its mostly a DMA engine to the DDR3 on-board, their repository also has scripts for Linux I believe to test it.

All I know is I can't wait to get the Acorns I got since the XC7A200T is MUCH more roomy than the XC7A100T
I was attempting to get a RiscV core on a XC7A100T and man... Just the core and DDR controller would fit but had issues reaching timing... On the 200T it JUST worked^TM.
Whether or not it actually works in hardware is yet to be seen but its a LOT more promising than having like a -100ns slack on a million signals...

[Fred27]

Thanks. I wasn't expecting the Nitefury example to do much without being connected to PCIe - I just grabbed something to check I could push the bitstream over JTAG. I was happy to see it run and blink some LEDs connected to the expected pins. It gave me more confidence that it's the same device.

Thanks for the info about clocks. I'm very much a FPGA beginner, so might just get my head round what's where and blink some LEDs using the onboard clock first before plugging it in to a PCIe slot.

[asmi]

The limitation is that there is only one on-board clock on the NiteFury/Acorn, a 200Mhz DDR clock. Theoretically you can use that DDR clock for other stuff internally and even to generate the 100Mhz PCIe clock if your going to say run PCIe in host mode and want to spit out a 100Mhz ref. But its a bit of a learning curve where you can use the internal buffers and where you can't.

As I understand you aren't going to be able to route clock from fabric into MGT's PLL. So your best bet would be to build a simple board with PCIE connector and place a clock generator there. This clock is probably also used for M.2 connector's PCIE (or SATA) interface.

[miken]

Phew, this thing makes a really annoying squeal I wonder if a bigger fan can be shoehorned on.

So I was able to connect it up to my Xilinx dongle and dump the flash. The markings on the flash chip are
S25FL256
SAVH20
which I believe corresponds to ordering part S25FL256SAGBHV20. It's 256 Mb, 133 MHz, 105 degC, 64 kB sectors.

I also loaded in my "Hello World" image that blinks the 4 LEDs, and discovered that I'd forgotten to invert the polarity. I wasn't brave enough to try writing the flash yet.

I started a repo on Github with my barebones project: https://github.com/mng2/AcornCLE215p/
It's licensed under CERN Open Hardware License v2 Weakly Reciprocal, which is kind of like LGPL in spirit.

[conmega]

Phew, this thing makes a really annoying squeal I wonder if a bigger fan can be shoehorned on.

So I was able to connect it up to my Xilinx dongle and dump the flash. The markings on the flash chip are
S25FL256
SAVH20
which I believe corresponds to ordering part S25FL256SAGBHV20. It's 256 Mb, 133 MHz, 105 degC, 64 kB sectors.

I also loaded in my "Hello World" image that blinks the 4 LEDs, and discovered that I'd forgotten to invert the polarity. I wasn't brave enough to try writing the flash yet.

I started a repo on Github with my barebones project: https://github.com/mng2/AcornCLE215p/
It's licensed under CERN Open Hardware License v2 Weakly Reciprocal, which is kind of like LGPL in spirit.

Awesome! Glad to hear your making progress hacking on it.
Also interesting to know there is twice the size of flash on these compared to what NiteFury claims to put on, only 128Mb parts...
I just re-watched and scrubbed through that YouTube video again, looks like the DDR3 chip is "D9SHM":
https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k512m16ha-125
Which matches the size NiteFury specs and matches the defined part in their example program.
This is not a default part in Vivado, so I copied the timing information out of the defined Mig7 controller from their example project to make my life easier.
You should also be-able to export the pin map file (.ucf) from that example project's controller too. Which then allows you to simply import into your own project.

Also NOTE when your editing a MIG 7 controller, on the "Memory Options" panel the "Input Clock Period" ALWAYS re-calculates/resets to the memory clock (in this case their example is set to 1875ps/533Mhz) you will need to set this to 5000ps/200Mhz (if using the 200Mhz input DDR clock) EVERY TIME you go into the Mig7 config and change something and want to save it...
Usually you don't have to change anything if you set it up correctly the first time, but just a "trap for young players" as they say.

I got my boards in today
Just waiting on my Digikey order... Hopefully USPS gets them here by Thursday as they say they will.
I did plug them in to a system and they do seem to come alive and enumerate under linux as what they are so they at-least seem to work

I for now at-least have some Risc V cores Implemented with no timing issues with a PCIe root complex and Mig7 controller.
Here's to hoping I can get one of those alive when I get my cables!

[miken]

Hey conmega, sounds like you're working on something ambitious. A RISC-V computer system?

Thanks for looking up the memory. That looks like the right size part, 8 Gb, but the listing says D9STQ. I wonder if they are running at DDR3 1.5V instead of DDR3L 1.35V?

The MIG dialogs are indeed super annoying. We have a project at work with three memory banks... I was able to convert that project to IP generation from MIG .prj file and TCL.

Good luck with your project. My PCIe extender has arrived but it's 1x. Time to see if my old computer is still functional.

[conmega]

Yea, it is quite ambitious. I'll probably be lucky to get one 64-bit core going at 50~Mhz or so it looks like.
But hey if I can get that up alone that would be great.

Looking to heavily utilize Virtual I/O and BSCAN to JTAG adapter to allow for on chip debugging of internal signals without the need to break them out to headers. Likely going to break out only the things that make sense like say serial for a console so I can have that open live on another window.

The example program has the ram set for 1.5V not DDR3L...
And that chip part number I got off the youtube video of someone taking the heatsink off theirs so I believe the D9SHM is correct.
I also have had the example code programmed onto a board and according to the LEDS had the memory train properly.
So copy whats in the NiteFury example project and you should be OK.

Digikey order JUST got in today and I was able to make up all my cables.

I also ordered the parts for the little itty 20-pin connector and its not a male/female pin header like standard connectors. The cable side has two surfaces that show through the plastic housing so my idea to hack these together is by soldering.
Using 28awg wire I have had some success.
Basically my process is as follows (NOTE: keep pins on steel pin strip until the last step, do not break them off beforehand otherwise they will likely end up in the oblivion):
Needle nose pliers to get side crimp parts bent inwards and get them parallel so they will fit width wise into connector.
Take flush cutters and perpendicular to the pin cut the top most bits of the rear cable holding crimp off to allow pin to fit height-wise into the housing.
Then tape the strip down, get your cut/stripped 28awg wire, lay it in the channel and with very fine solder just flow the slightest amount in.
Also keep the wire just up to the tip of the front most crimp (towards the pin end) don't go further than that since this is where a plastic detent falls to hold the pin in the housing.
Any extra solder on the outside of the pin or too much on top of the wire will cause the pin not to fit... Its pretty tight!

But buying plenty of extra pins and a few extra housings will probably allow you to get together a complete cable with an hour or two of frustration under the microscope if you have one. If not maybe 2-3 hours and twice as many extra pins

Housing: https://www.digikey.com/product-detail/en/hirose-electric-co-ltd/DF52-20P-0.8C/H125095-ND/5721350
Pins: https://www.digikey.com/product-detail/en/hirose-electric-co-ltd/DF52-2832PCF/H125109CT-ND/5721384

[miken]

You work fast I took one look at those tiny crimp pins when they arrived, and set them aside for another day. Don't have magnification handy so I may put it off until I do.

Good to hear that the memory layout seems to match the NiteFury. I am distracting myself a bit, getting better acquainted with the PCIe core than I have needed to in the past.

[conmega]

That's good! I have been avoiding the PCIe core a bit after attempting to poke at it and realizing the example code in the NiteFury repository requires a certain linux kernel for the DMA example of the kernel module...
I do need to poke at a more simple PCIe endpoint and see how bad it is to just poke at simple registers.

I have been also working on designing a PCB to plug the little Acorn into that breaks to an x16 slot (x4 logically of-course) along with on-board 3.3V regulation and a 100Mhz HCST PCIe refclock.
This is in hopes that I can run a PCIe root complex off the FPGA and be-able to attach devices to it.
I have a lot of learning to do about differential signaling and AC/DC coupling some of these clocks. Luckily a lot of the clock chips and buffer chips have quite a few examples in them so we will see what comes of that.

[conmega]

Well I was able to get a RiscV32 core up on the FPGA and point the JTAG interface for it to the other 6-pin connector.
And OpenOCD was able to see it!

Code: [Select]

openocd.exe -f share\openocd\scripts\interface\jlink.cfg -c "adapter speed 10000" -c "transport select jtag"
Open On-Chip Debugger 0.10.0 (2020-05-03) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz

jtag
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46
Info : Hardware version: 8.00
Info : VTarget = 3.267 V
Info : clock speed 10000 kHz
Warn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!
Info : JTAG tap: auto0.tap tap/device found: 0x13039a73 (mfg: 0x539 (<unknown>), part: 0x3039, ver: 0x1)
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 5 -expected-id 0x13039a73"
Warn : gdb services need one or more targets defined
Also I have found there is a very simple modification that can be done to make your "2.5V LVDS" pins which are just 2.5V GPIO in the current config, there is nothing in the datasheet saying they HAVE to be LVDS they are just routed for it.
But there is a regulator in the schematics (U11) which is the 2.5V 500mA regulator for that rail... Its just feeling the Vref for that I/O bank and as far as I can tell that I/O bank is ONLY being used for those LVDS pins. (Might need to double check this for yourself)
So if you de-solder U11 and bridge Vin and Vout... You'll have 3.3V GPIO on those other 8 pins
Here is the regulator in question:
http://www.ti.com/lit/ds/symlink/tps82695.pdf

Cute little thing!
U11 is the right one of those regulators on the back of the SQRL (M.2 connector down) towards the bottom of the board.

From the pin-out of the datasheet Vin/Vout are BGA pads right in a row. So should be easy to bridge!

I serve no warrenty for your SQRL if you preform this modification! 
I would double-triple check the schematics before. But figured some might want to know this is a possible way to get 8 more 3.3V pins to go with your 4 other pins for a total of 12 3.3V I/O pins or 6 diff pairs

[justinjja]

I have a few of these CLE-215 fpgas.
They aren't rip offs, nitefury is SQRL's design. Dave Reynolds works for SQRL.

Adding a couple pictures w/ the heatsink removed if anyone is interested.