SRAM timing

[gpr]

Hi. Question about sram timing for ice40-based fpga board.

Clock is 100Mhz (10ns)

Here is a piece of verilog code, which reads every word from sram and do some tests on it: https://github.com/gproskurin/learning/blob/c1235d21a55309f51fe143deb23f783f5546f175/embedded/fpga_test/src/sram_test.v#L89-L129


It spends 3 cycles (10ns each) to read and process one value from SRAM:

• write sram address to some fpga register, optionally check previous data in "data copy register"
• wait one 10ns cycle
• latch data from SRAM data lines to fpga "data copy register", goto 1

Timing diagram for sram chip says, that data lines contain valid data 10ns after address is set on address lines.

I'm wondering is it possible to spend 2 cycles for each address:

• use data from sram data lines, update fpga address register with the next address at the same time
• wait 1 cycle, goto 1

I tested it and it works without any errors, but I suspect that I'm just lucky enough that my code timings fit, it seems it is not guaranteed.
For example, if I change address register and use data from data lines at the same time, I rely on data hold time (tOH) which is 3ns, but 3ns can be insufficient to process old data or latch it.
This is 2-cycles code, which works, but I'm not sure about it: https://github.com/gproskurin/learning/blob/2fa53b832005f817e942e5689e60af3b52bd38db/embedded/fpga_test/src/sram_test.v#L92-L121

Any thughts?

I have the same question about writing, but we can talk about reading for now.

SRAM chip datashit: https://www.olimex.com/Products/_resources/ds_k6r4016v1d_rev40.pdf

[Someone]

Timing diagram for sram chip says, that data lines contain valid data 10ns after address is set on address lines.

I'm wondering is it possible to spend 2 cycles for each address:

• use data from sram data lines, update fpga address register with the next address at the same time
• wait 1 cycle, goto 1

I tested it and it works without any errors, but I suspect that I'm just lucky enough that my code timings fit, it seems it is not guaranteed.
For example, if I change address register and use data from data lines at the same time, I rely on data hold time (tOH) which is 3ns, but 3ns can be insufficient to process old data or latch it.

You've identified the two parameters in play here tOH > 3ns and tAA < 10ns

But, the "code" does not make the timing. The tOH could be 0ns (or even negative) and an FPGA could still capture the data. What's missing are the timing constraints that allow the FPGA tools to do this work for you.

[gpr]

Timing diagram for sram chip says, that data lines contain valid data 10ns after address is set on address lines.

I'm wondering is it possible to spend 2 cycles for each address:

• use data from sram data lines, update fpga address register with the next address at the same time
• wait 1 cycle, goto 1

I tested it and it works without any errors, but I suspect that I'm just lucky enough that my code timings fit, it seems it is not guaranteed.
For example, if I change address register and use data from data lines at the same time, I rely on data hold time (tOH) which is 3ns, but 3ns can be insufficient to process old data or latch it.

You've identified the two parameters in play here tOH > 3ns and tAA < 10ns

But, the "code" does not make the timing. The tOH could be 0ns (or even negative) and an FPGA could still capture the data. What's missing are the timing constraints that allow the FPGA tools to do this work for you.

Probably there is some misunderstanding here, may be my question wasn't clear enough. By timing I mean inserting wait states (10ns) here and there, not sub-10ns times for logic propagation delays

• tOH is "output hold" time. This is how long sram chip still holds previous data on data lines if address is changed on address lines. Obviously it cannot be negative for sane sram chip: it won't change data on data lines before address is changed on address lines. And "min 3ns" means it is guaranteed to hold old data for 3ns after address change, after 3ns there is no garantee. For me, it means, if I change address for new data and read old data at the same time, I have only 3ns to read old data. I suspect this is where I should put timing constraint in my code if I use 2-cycle version
• tAA is <= 10ns, for code it means to wait at least 10ns (1 clock) after address lines changed until data lines hold new valid data. But before "address lines changed", that change should propagate from fpga register to output pin, which means another cycle wait. So it seems it is just impossible to do better than 2 cycles data access

[Someone]

tAA is <= 10ns, for code it means to wait at least 10ns (1 clock) after address lines changed until data lines hold new valid data. But before "address lines changed", that change should propagate from fpga register to output pin, which means another cycle wait. So it seems it is just impossible to do better than 2 cycles data access

You are still thinking that the "code" is needing to wait for the propagation. How long does it take for the address line to change after the internal register is set? how long does it take for the data output of the SRAM to arrive at the r_sram_data_copy register?

Those are the things which timing constraints will control (bound), and the tools will report if the constraint can be satisfied. Then there is no ambiguity as to will it work with 1 cycle delay or does this need 2 cycles access time.

Obviously it cannot be negative for sane sram chip

But setup and hold times can be negative in the FPGA, so even a 10ns tAA could be captured by an FPGA on the next clock edge of a 10ns clock (even after including propagation delays).