STA timing closure for asynchronous FIFO

[promach]

I have implemented an asynchronous FIFO

However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.

Both read_clk and write_clk are having the same clock frequency.

Could anyone advise ?

[hamster_nz]

It you are using Vivado, I suggest using the XPM clock crossing macros where possible. They have embedded constraints so you don't have to fiddle with constraints or attributes yourself.

Makes life so much easier.

I know that you most likely have your own clock domain crossing solution, but there are quite a few gotchas lurking - like the correct use of the 'async_reg' attributes...

[ejeffrey]

Definitely use the vendor macro if available.  They will provide the most efficient implementation for the specific platform.

I'm not sure how other tools work exactly, but in Quartus for instance, synchronizer chains for CDC between unrelated clock domains are automatically detected and protected from optimization, and they automatically creates a false path constraint for timing analysis.  However, if the launch and latch clocks are the same or have a fixed phase relationship it will just treat it as standard logic.  The synthesizer has no way to recognize this as a correct async FIFO implementation that never reads and writes the same location at the same time, so it has to check timing as if you could.  The solution is to either add the proper timing directives or to use the platform macros and it is definitely better to use the macros when possible.