Author Topic: Status of unprogrammed FPGA  (Read 733 times)

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Offline mriPaul

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Status of unprogrammed FPGA
« on: April 28, 2020, 04:30:12 pm »
I have a Deo Nano SoC Developer's board. It is connected to another device using a PCB. The developer's board has 72 GPIOs and about 20 pins are talking to the other device. To be safe, I set all pins initially to open state and added a flag value such as the following using VHDL code:

gpio_0_inout(0) <= 'Z'; -- SCK(0)    when flag = 3  else 'Z';

It puts a pin in a high impedance state. I do this for all pins so I know the initial state and to avoid "back powering" other devices if they are not powered.

What is the state of the pins when the Deo Nano SoC is powered before I load a program?




 

Offline nctnico

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Re: Status of unprogrammed FPGA
« Reply #1 on: April 28, 2020, 04:46:36 pm »
avoid "back powering" other devices if they are not powered.
If this is your goal you need special buffers (in seperate chips) or check the datasheet to see whether the pins can be used for this situation.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline SiliconWizard

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Re: Status of unprogrammed FPGA
« Reply #2 on: April 28, 2020, 04:58:43 pm »
What is the state of the pins when the Deo Nano SoC is powered before I load a program?

Maybe someone here knows, but otherwise you should check out the datasheet of the FPGA that's used on this board. It should be stated in there.
I think it's common on many FPGAs that most IOs be in high impedance upon power on/configuration, but I can't guarantee this to be true for ALL.
 
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Offline hamster_nz

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Re: Status of unprogrammed FPGA
« Reply #3 on: April 29, 2020, 01:51:15 am »
From 11-2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

Quote
I/O Pins Remain Tri-stated During Power-Up

The output buffers of Cyclone IV devices are turned off during system power up or
power down. Cyclone IV devices do not drive out until the device is configured and
working in recommended operating conditions. The I/O pins are tri-stated until the
device enters user mode.

The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are
always enabled (after POR) before and during configuration. The weak pull up
resistors are not enabled prior to POR.

Not siure about Cyclone IV, but on other vendors/parts the bitstream generation phase has options to set the state of unused I/O pins, which defaults to input with a weak pull-up on Xilinx, IIRC.

This is so the input buffers on unused pins are not left floating in the breeze.
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Offline Daixiwen

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Re: Status of unprogrammed FPGA
« Reply #4 on: April 29, 2020, 07:31:29 am »
Yes you can set the state of the unused pins after configuration in Quartus, and by default they are in tristate with a weak pull-up.
 
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Offline AndyC_772

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Re: Status of unprogrammed FPGA
« Reply #5 on: April 29, 2020, 10:13:20 am »
Note also that assigning them 'Z' in your code really does mean high impedance, ie. the internal pull-up is disabled and the pin will float (unless you explicitly enable the weak pull-up in the assignment editor, IIRC).

IIRC Altera actually recommend setting unused pins as outputs driving low.

Offline SiliconWizard

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Re: Status of unprogrammed FPGA
« Reply #6 on: April 29, 2020, 01:27:45 pm »
Note that it really depends on each vendor...
For Xilinx you can refer to this: https://forums.xilinx.com/t5/Design-Entry/Unassigned-Pin-Behavior/td-p/34114
So, the default for unused pins in your design is they get pulled down. No need to do anything explicitly.

Also note that if the default behavior at power on for a particular FPGA is a weak pull-up, pins may be able to power other components connected to them through the pull-ups (with granted a very low current), which is unlikely to cause any damage but could cause weird behaviors with some components that are very low power.
 
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Offline amyk

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Re: Status of unprogrammed FPGA
« Reply #7 on: April 30, 2020, 12:14:31 am »
Also note that if the default behavior at power on for a particular FPGA is a weak pull-up, pins may be able to power other components connected to them through the pull-ups (with granted a very low current), which is unlikely to cause any damage but could cause weird behaviors with some components that are very low power.
Unless there is no top ESD diode, you can always "backfeed" through an I/O.
 
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Offline NorthGuy

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Re: Status of unprogrammed FPGA
« Reply #8 on: May 08, 2020, 11:43:02 pm »
I know Xilinx FPGAs have a special pin which either disables or enables pull-ups on unconfigured FPGA. Of course, once you configure it, everything depends on your design.
 

Online asmi

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Re: Status of unprogrammed FPGA
« Reply #9 on: May 09, 2020, 03:12:08 am »
I know Xilinx FPGAs have a special pin which either disables or enables pull-ups on unconfigured FPGA. Of course, once you configure it, everything depends on your design.
Yep, PUDC_B pin. For configured state, there is a bitstream option which allows setting a state of unused IOBs - could be pulldown, pullup, or none/floating.

Offline filssavi

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Re: Status of unprogrammed FPGA
« Reply #10 on: May 09, 2020, 06:07:25 am »
It’s been a while since I used the DE0 but before programming the pins are all pulled to 1 by a weak pull-up,and there is no ready way to change that, this  is also the default for intel and lattice as said before with Xilinx there is a pin, depending upon its voltage the others are pulled up or down at boot, however this is by far the exception and not the rule, also usually the dev boards don’t make it easy to change setting (no jumpers or solder bridges, usually just a non descript 0402 resistor somewhere)

This is a big trap for first time users, that are used to IC’s with sane defaults (everything off or tristate unless I say so)

The reason this is done is for power consumption, using all pins to ground default will increase it considerably (somewhere in the range of 2x to 5x IIRC) I don’t know why for sure but my theory is that there is more internal leakage current when the pin is at 0 than otherwise
 

Online OwO

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Re: Status of unprogrammed FPGA
« Reply #11 on: May 09, 2020, 06:49:01 am »
Something to do with PMOS having higher leakage because more area is needed to get the same on resistance?
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Offline filssavi

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Re: Status of unprogrammed FPGA
« Reply #12 on: May 09, 2020, 07:52:51 am »
Something to do with PMOS having higher leakage because more area is needed to get the same on resistance?

Yea that sounds very plausible , especially with the same driving voltage
 


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