Electronics > FPGA

Streaming data FPGA interface -> off the shelf?

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jevinskie:
You might like this Atrix 7 35k paired with a FX3: https://m.aliexpress.com/item/1000006618157.html

FlipFlop10:

--- Quote from: NorthGuy on January 09, 2022, 06:53:36 pm ---The FT601 FPGA FIFO interface is rather straightforward. The timing requirements in their documentation are very strange. They require huge hold time (4.8 ns) which is absolutely impossible to meet. They have an XDL example where they "forgot" to put minus - they have "set_output_delay -min 4.8" instead of "set_output_delay -min -4.8". This certainly passes timing analysis every time. But if you put the "minus" in, it's utterly impossible. Even though I had some help from the trace delay (400 ps), I could only meet 2.3 ns hold. This worked well at 100 MHz, buf failed at 66 MHz. From which I concluded that 4.8 ns is either bogus, or reflects only the worst case (66 MHz at 1.8V).

--- End quote ---
The timing diagrams show that you should use the falling edge of the clock to change data/control signals. However, the hold time is specified from the rising edge. With a period of 10 ns, you should be able to satisfy the hold requirement when launching data on the falling edge (5 ns delay) + clock to output delay and delay on your board. The output delay constraint is indeed nonsense

NorthGuy:

--- Quote from: FlipFlop10 on February 09, 2022, 06:03:22 pm ---The timing diagrams show that you should use the falling edge of the clock to change data/control signals. However, the hold time is specified from the rising edge. With a period of 10 ns, you should be able to satisfy the hold requirement when launching data on the falling edge (5 ns delay) + clock to output delay and delay on your board. The output delay constraint is indeed nonsense

--- End quote ---

The hold time (T4) is the time you must keep the data line stable after the rising clock edge. It is 4.8 ns. Then there's 4.2 ns window when you free to change the data. The new data must get stable 1 ns before the next clock, which is the setup time (T3).

4.8 + 4.2 + 1 = 10 (the period).

If you drive the data back straight from the IOB flop using the FTDI clock, this will be fast enough to meet the setup requirement, but the data may change whole lot faster than 4.8 ns. If you insert a delay to circumvent this, you will no longer be able to meet the setup requirement.

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