Structural design

[Tamas1992]

Hi,

I would like to practice logic design, preferably with real designs/projects.
To give an idea about my level here are some examples what I've done so far: 1 bit full adder, Gray code up counter, 3 bit up-down counter.
So fairly basic stuff, although I do not fear a good challenge.
I can implement combinational logic in Verilog (using ModelSim - Altera). (learning the behavioral modelling is in progress, I've used some aspects of it in testbenches already)
 
So if someone needs some logic functionality designed I'm happy to give it a try. (For FREE)

Best regards:
Tamas

[tggzzz]

I don't need anything done!

A suitable starting point is to design and implement a traffic light controller. Start with the basic red/amber/green sequence, then extend the design to include push buttons that allow pedestrians to cross.

Pay attention to designing the finite state machine (FSM) and then implementing it. Think about how the implementation could make it easier or more difficult to correctly extend the functions later.

[rstofer]

The LC3 (not LC3b) project that seems to be a popular project at many universities.  It implements a simple 16 bit RISC CPU.  Given the state transition diagram in Appendix C, the FSM is pretty easy to write.  The logic diagrams pretty much detail which components you need to create and how to interconnect them.  It's actually a pretty simple project.  A bunch of code is provided for testing.

https://www.cs.utexas.edu/users/fussell/courses/cs310h/lectures/Lecture_10-310h.pdf
https://www.cs.colostate.edu/~cs270/.Summer20/resources/PattPatelAppA.pdf
http://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/docs/LC3-uArch-PPappendC.pdf

The book is:
https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509

I haven't gotten around to the LC3b project which changes the CPU to include 8 bit addressing instead of 16 bit.  There are links on the Internet for this version.

[Tamas1992]

Traffic light control logic with adjustable delay between transitions:


Here is how I solved it:
4 states - 2 JK ffs
3 inputs from delay circuitry

There are 3 individual delay settings ( 1 for red, 1 for red-yellow and yellow, 1 for green)
3 x 32 bit delay registers, each get their value from a serial to parallel shift register
3 x 32 bit up counters
Entering a state starts the associated counter.
When the contents of a delay register and its associated counter register is equal, a trigger signal is set for the control logic and the FSM advances a state.
The delay idea is from a PIC Timer module with comparator functionality, which works the same way.