Switch between two inouts

[Prehistoricman]

I'm writing a PS/2 mouse driver and I would like to be able to switch the input signals, CLK and DATA, between a legit PS/2 port and a PS/2-USB bridge.

Into the top module I have both sets of signals defined, and my switch between USB and PS/2:

Code: [Select]

inout PS2_CLK, PS2_DATA;
inout USB_CLK, USB_DATA;
input SW15;
And these are connected to a mouse transceiver module that has a single pair of inouts for data and clk.
My naïve first attempt was this:

Code: [Select]

MouseTransceiver mt (
  .RESET(RESET),
  .CLK(CLK),
  .CLK_MOUSE(SW15 ? PS2_CLK : USB_CLK),
  .DATA_MOUSE(SW15 ? PS2_DATA : USB_DATA),
...
But this solution gives me multi-driven nets. I don't know how to write what I'm looking for.

[ataradov]

I don't think it is possible to do that in FPGA.

All inout stuff must happen in the pin driver on the top level.

So MouseTransceiver must have input, output and direction controls for both sides. And they will turn into inout signal later.

[Prehistoricman]

So MouseTransceiver must have input, output and direction controls for both sides. And they will turn into inout signal later.

Aha. So in the top module I'd had something combinational deciding, based on the data direction and switch, which signals to route.

This is what I came up with (it works):

Code: [Select]

assign CLK_MOUSE_IN =  SW15 ? PS2_CLK  : USB_CLK;
assign DATA_MOUSE_IN = SW15 ? PS2_DATA : USB_DATA;
 
//Disable USB outputs if SW15 asserted
assign USB_CLK  = SW15 ? 1'bZ : (CLK_MOUSE_OUT     ? 1'b0           : 1'bZ);
assign USB_DATA = SW15 ? 1'bZ : (DATA_MOUSE_OUT_EN ? DATA_MOUSE_OUT : 1'bZ);
//Disable PS/2 outputs if SW15 not asserted
assign PS2_CLK  = ~SW15 ? 1'bZ : (CLK_MOUSE_OUT     ? 1'b0           : 1'bZ);
assign PS2_DATA = ~SW15 ? 1'bZ : (DATA_MOUSE_OUT_EN ? DATA_MOUSE_OUT : 1'bZ);
It's unfortunate that I can't get this functionality with the inouts in the transceiver module. Do you know if that kind of thing would be possible in SystemVerilog or VHDL?

[ataradov]

It is not about the language. It is impossible in the FPGA fabric itself. Tri-state in-out signals only exist in the I/O cells. The rest of the logic must have defined direction.