Switching read & write between memory banks with a flag (verilog) - timing issue

[SMB784]

I have two memory banks A & B and a flag called "epoch" that tells my design to write to bank A and read from bank B if epoch=1 and to read from bank A and write to bank B if epoch=0.  Epoch changes from 0 to 1 or vice versa when a counter hits a certain threshold.

I have tried implementing this by just using an if-else statement in an always_ff block:

Code: [Select]

    logic [15:0] counter;
    logic epoch;
    always_ff @(posedge clk)
    begin
            if(counter[15]) epoch<=1;
            else epoch<=0;

            if(epoch)
            begin:write_A_read_B
                    wr_en_A<=1'b1;
                    wr_en_B<=1'b0;
            end
            else
            begin:read_A_write_B
                wr_en_B<=1'b1;
                wr_en_A<=1'b0;
            end

            counter<=counter+1'b1;
    end

This synthesizes just fine, and the elaborated design looks the way it should, but it complains at the implementation step because I am using a net as a clock pin or something like that.

So instead I instantiate a BUFGCE and use counter[15] as the input and clock enable pin and epoch as the output so that epoch goes high when counter[15]=1 and LOW when counter[15]=0:

Code: [Select]


    logic epoch;
    logic [15:0] counter;
    BUFGCE epoch_buffer
    (
            I(counter[15]),
            CE(counter[15]),

            O(epoch)
    );

    always_ff @(posedge clk)
    begin
            if(epoch)
            begin:write_A_read_B
                    wr_en_A<=1'b1;
                    wr_en_B<=1'b0;
            end
            else
            begin:read_A_write_B
                wr_en_B<=1'b1;
                wr_en_A<=1'b0;
            end

            counter<=counter+1'b1;
    end

This synthesizes just fine, the elaborated model works great, and it even obeys timing closure, but I get a critical warning in the Methodology section from Vivado with the following text "TIMING #1 Critical Warning The clock pin epoch_buffer/I is not reached by a timing clock ".  What does this mean?  Is there a better way of implementing my design that either doesn't need BUFGCE or uses it in a way that doesn't create this critical warning?

***EDIT*** Fixed the blocking assignment in the counter net, should written non-blocking.  It is implemented as non-blocking in my design. whoops

[FenTiger]

Where does "clk" come from? You might need to add a "create_clock" constraint to tell Vivado that it's a clock rather than a generic logic net.

[SMB784]

Where does "clk" come from? You might need to add a "create_clock" constraint to tell Vivado that it's a clock rather than a generic logic net.

I have done that, and it doesn't complain about clk. What it appears to be complaining about is the fact that the input to BUFGCE isn't a timing clock. I guess my question is, then, how do I alternate writing for bank A and bank B based on a certain counter threshold?

[NorthGuy]

I have done that, and it doesn't complain about clk. What it appears to be complaining about is the fact that the input to BUFGCE isn't a timing clock. I guess my question is, then, how do I alternate writing for bank A and bank B based on a certain counter threshold?

BUFG is a clock buffer. Why do you want to use it for a signal which is not a clock?

[SMB784]

I have done that, and it doesn't complain about clk. What it appears to be complaining about is the fact that the input to BUFGCE isn't a timing clock. I guess my question is, then, how do I alternate writing for bank A and bank B based on a certain counter threshold?

BUFG is a clock buffer. Why do you want to use it for a signal which is not a clock?

Fair enough, is there another buffer I can use that wont cause the compiler to complain about driving a write enable pin with a logic net?  I don't have much experience with buffering, and I am looking to alternate write enables between the two banks based on when a certain criteria is met (e.g. the counter hitting a certain number, or some other arbitrary threshold).

[asmi]

Fair enough, is there another buffer I can use that wont cause the compiler to complain about driving a write enable pin with a logic net?  I don't have much experience with buffering, and I am looking to alternate write enables between the two banks based on when a certain criteria is met (e.g. the counter hitting a certain number, or some other arbitrary threshold).

You can drive write enable with regular fabric routing without any dedicated buffering required.
Please post the full code if you want us to help. You say P&R complains about memory nets, yet I don't see any memory in the code you've posted.

Also - have you simulated the code and did a functional verification? Your code probably doesn't exactly work like you think it does because of non-blocking assignments.

[SMB784]

Fair enough, is there another buffer I can use that wont cause the compiler to complain about driving a write enable pin with a logic net?  I don't have much experience with buffering, and I am looking to alternate write enables between the two banks based on when a certain criteria is met (e.g. the counter hitting a certain number, or some other arbitrary threshold).

You can drive write enable with regular fabric routing without any dedicated buffering required.
Please post the full code if you want us to help. You say P&R complains about memory nets, yet I don't see any memory in the code you've posted.

Also - have you simulated the code and did a functional verification? Your code probably doesn't exactly work like you think it does because of non-blocking assignments.

Sure, I will clean it up and document it so its readable.  Also, I fixed the blocking assignment in the code I posted, its supposed to be a non-blocking assignment as it is in the actual design.  Not that it makes any difference.

[NorthGuy]

Fair enough, is there another buffer I can use that wont cause the compiler to complain about driving a write enable pin with a logic net?

I don't think you need any buffers. The problem is likely located somewhere else. I suggest you post the exact text of the error message.