Electronics > FPGA

Tang Nano 1K (Gowin FPGA) VGA output - artefacts, sync problem

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I built a module that emulates a DMD display from a pinball machine on a VGA monitor.
Device is based on Tang Nano 1K FPGA Module (GOWIN FPGA GW1N-1LV).
VGA ouput:
-16-bit RGB565 color(palette) depth,  (only 4 colors displayed simultaneously)
- high-speed R-2R resistor ladder DAC  (270/536Ohm)
- High-speed buffers (74ALVC245)
- 3 mode 800x600, 1024x768, 1152 X 864.

Everything works fine until I use colors that are different on all 16-bits (14/15-bit with some combinations), for example WHITE (0xFFFF) and BLACK (0x0000).
In such a situation, artifacts and problems with horizontal synchonization begin to appear on the screen.
If I select 0xFFDF and 0x0000 = OK, 0xFFFE and 0x0000 = OK,  0xF7FF  and 0x0000 = artefacts.

Current FPGA I/O pin configuration:   LVTTL33, SlewRate - Slow, Drive =4 mA (lowest possible)
With default configuration LVCMOS33, SlewRate-Fast, Drive=8mA the situation was much worse.

The problem occurs with all VGA resolutions.

I suppose the problem might be related to the power supply (spikes while switching multiple outputs simultaneously).
I powered output buffers  powered from an additional stabilizer - No improvement
Converting 5V power from USB to laboratory power supply -  No improvement
Additional capacitors at the stabilizers (I/O banks)  -  No improvement
Serial termination resistors (100 Ohm) between FPGA and output Buffer(ALVC245) - small improvment (Static image ok, but breaking synchronization with dynamic images).

Artifacts only appear on lines with full bit change.

Schematic of Tang Nano Modue:
R-2R Dac and driveres analogous to:

After all attempts, the greatest improvement is when I change the I/O pin configuration -  decrease pin Drive to 4 mA, lowest possible.

What else could I check and improve ?
Modifications on the Tang Nano module are difficult due to the very small SMD components .


My completely hypothetical reason is crosstalk between the colour channels and the sync channels.

Do you have picture of your DAC? Is it just flying wires & through-hole parts on a breadboard? Or are you using the PMOD?

This is probably not the problem here.
Sync signal are buffered by separate chip with separate power supply.
I also changed the cables between the module and the monitor .

I did an experiment and I delayed half the RGB signals by 2.7ns (IODELAY primitive DELAY=90*30ps) and it seems to have helped.
But it is 30% of pixel clock period (108MHz) and discoloration may be visible .

Oh, you have buffers in the middle? What part number?

If you have a spare PCB (everybody gets 5 or 10...) , maybe try building up a board but not populating and then bypassing the buffer footprint.

All boards that I have are fully populated.

But if I bypass buffers all current for DAC line will be sourced from FPGA I/O pins, which will further increase the load on the bank I/O power supply.


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