Tasks in Verilog on Clock edges

[Dmeads]

Hi,

I am trying to create a task to toggle a register on the negative edge of a clk;

I used a task (i dont think functions can model sequential stuff?)  that has some syntax errors, but I don't know what im doing wrong. Also, once the task is coded right, how do I call it in my initial block?

Code: [Select]

 
`timescale 1ns / 1ps

module tb;
  reg A,B,C,D,E,K;
  reg COMPLS6 = 0; // RD
  reg SBYTECLK = 0;
 
  always #2 SBYTECLK = ~SBYTECLK;
 
  encoder_5b6b uut(A,B,C,D,E,K,COMPLS6,SBYTECLK);
 
  task DISP;
    input SBYTECLK;
    begin
      always @ (negedge SBYTECLK)  // reverse RD
      COMPLS6 = ~COMPLS6;
    end
    endtask;
     
 
  initial
    begin  // test all possible 4-0, 0-4, 1-3, 3-1, and 2-2 one-zero combos
      $dumpfile("dump.vcd");
      $dumpvars(0,uut);
  SBYTECLK = 0;
      K = 0;  // Data only
      DISP();  // START RD @ 0 (-1);
      A = 1;
      B = 0;
      C = 0;
      D = 0;
      E = 0;
      #4
      A = 1;
      B = 1;
      C = 1;
      D = 0;
      E = 0;
      #4
      $finish;
    end
endmodule

[ejeffrey]

You can't use always inside a task, but you can call a task from inside an always or initial block.  It certainly wouldn't make sense in this situation as you then would have always inside an initial block.  This should probably be a module or maybe just a loop.

You call a task with normal "function call" syntax.