Techniques to measuring propagation delay of FPGA routes

[steamedhams]

I have been tasked to measure the propagation delay of FPGA routes.

From the googling I did, it appears I use a ring oscillator into another inverter, then compare the difference with the ring oscillator output arrival time with that of the inverter.

I have been given a circuit that should provide me with the delay. However, I cannot understand the OR gate timing graph.

Can anyone explain this??

[FenTiger]

I think that diagram is labelled wrongly. The time from the rising edge of I0 to the rising edge of I1 should be labelled 𝛿2H. The 𝛿2L label should apply to the time from the subsequent falling edge of I0 to the falling edge of I1.

Given that change, I think I understand the circuit: when the AND gate is selected, the LUT output goes high when I0 goes low, but doesn't go low until I1 goes high, so the oscillator period includes 𝛿2H but not 𝛿2L. Similarly, when the OR gate is selected, the LUT output goes low when I0 goes high, but doesn't go high until I1 goes low, so the period includes 𝛿2L but not 𝛿2H.