Electronics > FPGA

The NEORV32 Risc-V Processor

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dolbeau:

--- Quote from: DiTBho on July 07, 2022, 07:22:48 am ---Not mentioning that every single university project is multi-cycles-based rather pipeline-based.

--- End quote ---

The original Stanford MIPS was pipelined (became MIPS R2000).
The Berkeley RISC was pipelined (became SPARC).
Fast forward to the present, Ariane (became CVA6) and RI5CY (became cv32e40p) are pipelined.


--- Quote ---Not mentioning that every single project that aims for real-time and cycle-precision is multi-cycles-based rather then pipeline-based.

--- End quote ---

Even the smaller Arm Cortex-R, the R4, is pipelined.


--- Quote ---Not mentioning that every single project when you have to deal with pipeline needs "critic code" and instructions like { sync, isync, fence, ... } which (in every PowerPC  book) are described as "voodoo black magic code"

--- End quote ---

Those instructions are not required for pipelines, but for multiprocessors.

DiTBho:

--- Quote from: dolbeau on July 08, 2022, 09:32:21 am ---The original Stanford MIPS was pipelined (became MIPS R2000).
The Berkeley RISC was pipelined (became SPARC).

--- End quote ---

University projects like SPIM, MARS, and laboratory projects assigned to students: all multi-cycles!

DiTBho:

--- Quote from: dolbeau on July 08, 2022, 09:32:21 am ---Those instructions are not required for pipelines, but for multiprocessors.

--- End quote ---

Superscalars need them, as well as Multitreads need them

custom designs with non-superscalars and LIFO/FIFO memory mapped devices may need "pipeline-dedicate instructions" to mitigate.

Talking about the RISC-V ISA, there are implementations that use a "relaxed memory model" where the order of loads and stores performed by one thread may be different when seen by another. This is done to enable techniques to increase memory system performance.

Because again we are all obsessed by performance, aren't we? sure we are, and gain, FENCE is the only thing that can save your day.

brucehoult:

--- Quote from: DiTBho on July 08, 2022, 01:29:19 pm ---
--- Quote from: dolbeau on July 08, 2022, 09:32:21 am ---Those instructions are not required for pipelines, but for multiprocessors.

--- End quote ---

Superscalars need them, as well as Multitreads need them

custom designs with non-superscalars and LIFO/FIFO memory mapped devices may need "pipeline-dedicate instructions" to mitigate.

Talking about the RISC-V ISA, there are implementations that use a "relaxed memory model" where the order of loads and stores performed by one thread may be different when seen by another.

--- End quote ---

Not by another thread. By another CPU.

DiTBho:

--- Quote from: brucehoult on July 08, 2022, 11:59:34 pm ---Not by another thread. By another CPU.

--- End quote ---

Same CPU with resources replication

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