Electronics > FPGA

The NEORV32 Risc-V Processor

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--- Quote from: DiTBho on July 09, 2022, 01:13:22 am ---
--- Quote from: brucehoult on July 08, 2022, 11:59:34 pm ---Not by another thread. By another CPU.

--- End quote ---

Same CPU with resources replication

--- End quote ---

What do you mean by that?

RISC-V caches must appear to software [1] to be physically-indexed, physically-tagged, so even if another thread accesses the same RAM at a different virtual address the correct data is seen.

[1] many implementations use virtually-indexed L1 cache so the cache access can proceed in parallel with the TLB lookup, but as long as the associative "way" size is no larger than a VM page the effect it the same. i.e. a 16 KB L1 cache must have at least 4 ways, a 32 KB L1 cache must have at least 8 ways etc. L2/L3 cache waits for TLB so can have fewer ways.

The reasons for me to use this processor are in no particular order:
- Documentation is pretty good, as well as examples
- Support from the mantainer is top notch. I've been working with him this week in getting to execute code from an SPI flash on my dev kit by changing the bootloader. After a few misses and some bugs we found, it's working.
- Performance wise... we'll see... very early days still, but if I can get an audio signal ADC'd and DAC'd, that will be a good start.

With the above in mind, I've felt that other implementations are more "academic" oriented, if that makes sense, in terms of creating big constructs but in a more complex way, aimed at FPGA developers rather than ┬ÁC users/developers. It's fun to add a new peripheral to your micro, I love that flexibility, but after that's done some of us would want to just use the construct, flash a binary, debug the code, and be done with the project until the next one comes along.

The above is my opinion, based on observation. I'm not belittling the work other groups have done, I'm a big fan of open source, but at times it's very hard to get through the initial barrier in new projects.




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