Hi all,
I searched through the forum just to make sure I'm not repeating someone else's information, it turns out the term "neorv32" appears only once, on a post I made last year, and just in passing. As luck would have it, I was redirected to the NeoRV32 project in my interest to get a soft Risc-V processor into an FPGA. I'd looked at Litex, VexRiscV, PicoRV32, and while they were ok, documentation was either lacking, you'd need to invest A LOT of time to get something decent up and running, or dabble in Migen which is a Python way of describing hardware. Mainly it all felt a bit cumbersome.
But back on track, I went and looked into
https://www.neorv32.org/, and looked at both the user manual and the datasheet.
This is so far the best and most understandable Risc-V implementation I've come across. After investing some time in reading the details, I was able to have a program compiled and up and running in minutes, both in Xilinx and Altera dev kits. The community also seems very open to questions, somehow, and this is my own personal opinion, the documentation and help seem less obscure than some other open source projects I've come across.
The official repo has test examples based on hardware and software. There are a few simple tools that help you getting that C code flashed into the FPGA as well, so your design is persistent. All the code is well documented and very well written, IMO.
If you're looking to get a Risc-V processor running on an FPGA, have a look at this, a very good place to get started. I'm curious to see what you guys think if you get around to it.
Cheers,
Alberto